Zobrazeno 1 - 10
of 139
pro vyhledávání: '"On-chip Training"'
Autor:
Zeinolabedin, Seyed Mohammad Ali, Schüffny, Franz Marcus, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hänzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Höppner, Sebastian, Mayr, Christian
With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific res
Externí odkaz:
https://tud.qucosa.de/id/qucosa%3A89919
https://tud.qucosa.de/api/qucosa%3A89919/attachment/ATT-0/
https://tud.qucosa.de/api/qucosa%3A89919/attachment/ATT-0/
Autor:
Kyu-Ho Lee, Dongseok Kwon, In-Seok Lee, Joon Hwang, Jiseong Im, Jong-Ho Bae, Woo Young Choi, Sung Yun Woo, Jong-Ho Lee
Publikováno v:
Advanced Intelligent Systems, Vol 6, Iss 1, Pp n/a-n/a (2024)
Herein, dual‐gate field‐effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR‐type array designed for low‐power on‐chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notabl
Externí odkaz:
https://doaj.org/article/ad450379e244497fabd63822824ed7b8
Autor:
Tsung-Han Tsai, Ding-Bang Lin
Publikováno v:
IEEE Open Journal of Circuits and Systems, Vol 4, Pp 85-98 (2023)
In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other
Externí odkaz:
https://doaj.org/article/d8e22970b05147c0b4308a37c83818bf
Autor:
Jiseong Im, Jaehyeon Kim, Ho-Nam Yoo, Jong-Won Baek, Dongseok Kwon, Seongbin Oh, Jangsaeng Kim, Joon Hwang, Byung-Gook Park, Jong-Ho Lee
Publikováno v:
IEEE Access, Vol 10, Pp 31263-31272 (2022)
Artificial Neural Networks (ANNs) have shown remarkable performance in various fields. However, ANN relies on the von-Neumann architecture, which consumes a lot of power. Hardware-based spiking neural networks (SNNs) inspired by a human brain have be
Externí odkaz:
https://doaj.org/article/e08780653d1f45ceb66ccb75e2463b25
Autor:
Zeinolabedin, Seyed Mohammad Ali, Schüffny, Franz Marcus, George, Richard, Kelber, Florian, Bauer, Heiner, Scholze, Stefan, Hänzsche, Stefan, Stolba, Marco, Dixius, Andreas, Ellguth, Georg, Walter, Dennis, Höppner, Sebastian, Mayr, Christian
With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific res
Externí odkaz:
https://tud.qucosa.de/id/qucosa%3A82996
https://tud.qucosa.de/api/qucosa%3A82996/attachment/ATT-0/
https://tud.qucosa.de/api/qucosa%3A82996/attachment/ATT-0/
Autor:
Won-Mook Kang, Dongseok Kwon, Sung Yun Woo, Soochang Lee, Honam Yoo, Jangsaeng Kim, Byung-Gook Park, Jong-Ho Lee
Publikováno v:
IEEE Access, Vol 9, Pp 73121-73132 (2021)
A hardware-based neural network that enables on-chip training using a thin-film transistor-type AND flash memory array architecture is designed. The synaptic device constituting the array is characterized by a doped $p$ -type body, a gate insulator s
Externí odkaz:
https://doaj.org/article/6d947f076ca64bc18382de7c5266a9d3
Autor:
Wonbo Shim, Shimeng Yu
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 7, Iss 1, Pp 1-9 (2021)
Different from the deep neural network (DNN) inference process, the training process produces a huge amount of intermediate data to compute the new weights of the network. Generally, the on-chip global buffer (e.g., SRAM cache) has limited capacity b
Externí odkaz:
https://doaj.org/article/72c080190bf2417d8ed2e07a85dc9aa4
Akademický článek
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Akademický článek
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Autor:
Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min-Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee
Publikováno v:
Advanced Intelligent Systems, Vol 3, Iss 8, Pp n/a-n/a (2021)
On‐chip training of neural networks (NNs) is regarded as a promising training method for neuromorphic systems with analog synaptic devices. Herein, a novel on‐chip training method called direct gradient calculation (DGC) is proposed to substitute
Externí odkaz:
https://doaj.org/article/2ad44c2088ed41dcb455687719aea898