Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Oluwamuyiwa Oluwagbemiga Olubuyide"'
Autor:
Jayhoon Chung, Youn Sung Choi, Greg C. Baldwin, G Lian, Oluwamuyiwa Oluwagbemiga Olubuyide, Catherine Vartuli, Deborah J. Riley
Publikováno v:
IEEE Transactions on Electron Devices. 57:2886-2891
This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dba4280e927c907ae0095852df3d6ccc
https://doi.org/10.1109/ted.2010.2066567
https://doi.org/10.1109/ted.2010.2066567
Publikováno v:
2009 IEEE Dallas Circuits and Systems Workshop (DCAS).
For CMOS circuits, the increase in power consumption has been curtailed in recent years by introducing mechanical stress to achieve device speed gain over and above the traditional speed vs. power tradeoffs achieved only by scaling gate lengths. Star
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd9847ac38233413a629c53069e65c12
https://doi.org/10.1109/dcas.2009.5505728
https://doi.org/10.1109/dcas.2009.5505728
Autor:
Qi-Zhong Hong, Oluwamuyiwa Oluwagbemiga Olubuyide, James Walter Blatchford, Li Lin, Ricardo Borges, Steven L. Prins, T. S. Kim, Deborah J. Riley, Simon Chang
Publikováno v:
SPIE Proceedings.
As design rules and corresponding logic standard cell layouts continue to shrink node-on-node in accordance with Moore's law, complex 2D interactions, both intra-cell and between cells, become much more prominent. For example, in lithography, lack of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb495412ea5ac987bfae30e49a5e1d31
https://doi.org/10.1117/12.814947
https://doi.org/10.1117/12.814947
Autor:
Shaofeng Yu, Brian K. Kirkpatrick, O'brien Corey Rollin, Larry Liu, Rajesh Khamankar, Oluwamuyiwa Oluwagbemiga Olubuyide, Deborah J. Riley, Anand T. Krishnan, I. Fujii, C. Machala, Clinton L. Montgomery, Brian Hornung, H. Bu, Yiming Gu, Steven L. Prins, T. Lowry, K. Kirmse, James Walter Blatchford, Tad Grider, C. Bowen, G. Shinn, D. Corum, C. Lin, Tony Tae-Hyoung Kim
Publikováno v:
2008 Symposium on VLSI Technology.
A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect gene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e24ec331746ae0843044248c5da8aaa5
https://doi.org/10.1109/vlsit.2008.4588608
https://doi.org/10.1109/vlsit.2008.4588608