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pro vyhledávání: '"Olivier Burg"'
Autor:
Xiang Gao, Cao-Thong Tu, Haisong Wang, Konstantinos Manetakis, Mustafa Yayla, Luns Tee, Sining Xiang, Fan Zhang, Olivier Burg, Li Lin, Randy Tsang, Wanghua Wu
Publikováno v:
ISSCC
High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs. The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high-frequency VCO and converts phase/timing error into voltage. The steep dv/dt slope
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f1fdda6eba7b2f3819afba9749d7a66
https://doi.org/10.1109/isscc.2016.7417963
https://doi.org/10.1109/isscc.2016.7417963
