Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Olivier Billoint"'
Autor:
Thomas Bauvent, Paola Trotti, Olivier Billoint, Jean-François Nodin, Yasser Moursy, Gabriel Molas, Gaël Pillonnet
Publikováno v:
IEEE Electron Device Letters
IEEE Electron Device Letters, In press, pp.1-4. ⟨10.1109/LED.2023.3274219⟩
IEEE Electron Device Letters, In press, pp.1-4. ⟨10.1109/LED.2023.3274219⟩
International audience; Embedded resistive random access memories (RRAM) are commonly written using voltage programming scheme. In this work, we study the device performance under an alternative programming approach. Utilizing the parasitic line capa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9ce1bb4f8ac1892ae29349fdbf5bdd31
https://hal.science/hal-04115343/file/manuscript_doi_and_copyright.pdf
https://hal.science/hal-04115343/file/manuscript_doi_and_copyright.pdf
Autor:
Jerome Juillard, Chuan Shan, Elena Blokhina, Anton Korniienko, Eric Colinet, M. Javidan, Eldar Zianbetov, Olivier Billoint, Francois Anceau, Dimitri Galayko
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩
IEEE Transactions on Circuits and Systems II: Express Briefs, Institute of Electrical and Electronics Engineers, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩
IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩
IEEE Transactions on Circuits and Systems II: Express Briefs, Institute of Electrical and Electronics Engineers, 2019, 66 (10), pp.1673-1677. ⟨10.1109/TCSII.2019.2932029⟩
This brief presents an active distributed clock generator for manycore systems-on-chip consisting of a $10\times 10$ network of coupled all-digital phase-locked loops, achieving less than 38 ps phase error between neighboring oscillators over a frequ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2602071fab925a1aa2e01aeebedcb60c
https://hal.science/hal-02318785
https://hal.science/hal-02318785
Publikováno v:
ECS Transactions. 66:315-322
Ultra Thin Body and Box Fully Depleted Silicon-on-Insulator (UTBB FDSOI) devices are promising candidates to substitute planar CMOS technology for very large-scale integrated (VLSI) circuits, recently proved to implement complex systems [1]. Their ma
Autor:
T. Kauffmann, Ricardo Escola, Lionel Rousseau, Jean-Pierre Rostaing, Jean-Francois Beche, Olivier Billoint, Blaise Yvert, Cyril Condemine, G. Charvet, Stéphane Bonnet, Régis Guillemaud, Timothée Levi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9887548199f818c774c4b5813d04ab89
https://doi.org/10.1201/b11205-6
https://doi.org/10.1201/b11205-6
Autor:
Bruno Mercier, Celine Moulin, Jean-Pierre Rostaing, Serge Spirkovitch, Hervé Fanet, Lionel Rousseau, Philippe Chauvet, François Goy, Sébastien Joucla, G. Charvet, S. Gharbi, Mikael Colin, Blaise Yvert, Michel Trevisiol, Olivier Billoint, Alain Bourgerette, Pierre Meyrand, Régis Guillemaud
Publikováno v:
Biosensors and Bioelectronics. 25:1889-1896
Microelectrode arrays (MEAs) offer a powerful tool to both record activity and deliver electrical microstimulations to neural networks either in vitro or in vivo. Microelectronics microfabrication technologies now allow building high-density MEAs con
Publikováno v:
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, IEEE-CASS, Jun 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182059⟩
NEWCAS
New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, IEEE-CASS, Jun 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182059⟩
NEWCAS
International audience; This paper presents a Cartesian network of CMOS oscillators distributed on a chip and synchronized by a network of all-digital PLLs in phase and in frequency. Such a network may be used for generation of a global clock in larg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fb978180b6a2a62b9952e5640ef628ba
https://hal.archives-ouvertes.fr/hal-01521883
https://hal.archives-ouvertes.fr/hal-01521883
Publikováno v:
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732295⟩
ReConFig
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732295⟩
ReConFig
International audience; In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and recon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fdd1c675df50cad63aadf06306255ab5
https://hal.sorbonne-universite.fr/hal-01053762/document
https://hal.sorbonne-universite.fr/hal-01053762/document
Autor:
Dimitri Galayko, J. M. Akrea, Eldar Zianbetov, E. Colinet, Olivier Billoint, Francois Anceau, M. Javidan, Anton Korniienko, Chuan Shan, G. Scorletti, Jerome Juillard
Publikováno v:
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference
CICC 2013-IEEE 2013 Custom Integrated Circuits Conference
CICC 2013-IEEE 2013 Custom Integrated Circuits Conference, Sep 2013, San José, CA, United States. pp.1-4, ⟨10.1109/CICC.2013.6658437⟩
CICC
CICC 2013-IEEE 2013 Custom Integrated Circuits Conference
CICC 2013-IEEE 2013 Custom Integrated Circuits Conference, Sep 2013, San José, CA, United States. pp.1-4, ⟨10.1109/CICC.2013.6658437⟩
CICC
International audience; This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating syn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::77eaffae08efa4dfaa51eb01da53d6a1
https://hal.sorbonne-universite.fr/hal-01053768/document
https://hal.sorbonne-universite.fr/hal-01053768/document
Autor:
Jani Makipaa, Olivier Billoint
Publikováno v:
ISCAS
Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) . IEEE Institute of Electrical and Electronic Engineers, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13 . https://doi.org/10.1109/ISCAS.2013.6571903
Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) . IEEE Institute of Electrical and Electronic Engineers, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13 . https://doi.org/10.1109/ISCAS.2013.6571903
Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of
Autor:
J.P. Richer, Olivier Monnet, Jean-Pierre Rostaing, Arnaud Peizerat, O. Rossetto, Olivier Billoint, G. Montemont, J. Bouvier
Publikováno v:
2009 Conference Record IEEE
2009 IEEE Nuclear Science Symposium and Medical Imaging Conference
B. Yu. 2009 IEEE Nuclear Science Symposium and Medical Imaging Conference, Oct 2009, Orlando, United States. IEEE, pp.327-330, 2009
2009 IEEE Nuclear Science Symposium and Medical Imaging Conference
B. Yu. 2009 IEEE Nuclear Science Symposium and Medical Imaging Conference, Oct 2009, Orlando, United States. IEEE, pp.327-330, 2009
ISBN 978142443962; International audience; In this paper, we present two circuits designed for pulse readout of a semiconductor PET system: a fast low noise low power front-end preamplifier/shaper, and the processing circuit performing time tagging,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5253d65982242e16cd912b501e7683a8
http://hal.in2p3.fr/in2p3-00426390
http://hal.in2p3.fr/in2p3-00426390