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of 11
pro vyhledávání: '"Oliver Ansell"'
Autor:
Janet Hopkins, Taku Umemoto, Takuo Nishida, Martin Hanicinec, Oliver Ansell, Lijie Li, Harry Fulton
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:694-703
The main objective of this article is to establish which of the many dicing tapes used in the semiconductor industry would be most suitable for use in plasma dicing. Tape design over the past 40 years has continually evolved through advancements in b
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
Plasma dicing, as a means of isolating individual integrated circuits from within a fully processed semiconductor substrate, is still an emerging technology but is now considered the latest step in the evolution in device singulation. With the trend
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
A key driving force within the consumer electronics industry has always been to fit more functionality into a smaller area, and with the evolution of mobile communications and wearable devices, there are no signs of this requirement diminishing. This
Autor:
Huma Ashraf, Edward Walsby, Fumihiro Inoue, Oliver Ansell, Anne Jourdain, Kenneth June Rebibis, Andy Miller, Janet Hopkins, Joeri De Vos, Gerald Beyer, Dave Thomas, Jash Patel, Eric Beyne
Publikováno v:
3DIC
As the 3D interconnect density is increasing exponentially when scaling to lower levels of the interconnect wiring, we see that very soon 3D interconnect pitches of 5 μm and below will be required. Current 3D-SIC (3D-Stacked IC) technologies do not
Autor:
Eric Beyne, Huma Ashraf, Joeri De Vos, Jash Patel, Fumihiro Inoue, Oliver Ansell, Erik Sleeckx, Dave Thomas, Janet Hopkins, Akira Uedono, Anne Jourdain
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Wafer-to-wafer 3D integration has a potential tominimize the Si thickness, which enables us to connectmultiple wafers with significantly scaled through-Si vias. Inorder to achieve this type of 3D structure, backside thinningis a key step. Conventiona
Autor:
Moshe Kriman, Hagit Gershtenman-Avsian, Dorleta Cortaberria Sanz, Oliver Ansell, Hefin Griffiths, Matthew Muggeridge, Andrey Grinman, Dave Thomas, Mike Steel
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2011:002254-002271
Miniature, high performance camera modules are found in a range of consumer devices including phones, PDAs, cameras and gaming consoles. According to Gartner the $1B image sensor market will grow to $2.3B by 2013. Image sensor packaging technologies
Singulation by Plasma Etching: Integration Techniques to Enable Low Damage, High Productivity Dicing
Publikováno v:
Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales.
Plasma dicing has rapidly gained traction as a viable alternative to conventional blade and laser techniques for wafer singulation. This has been due mostly to the significant benefits plasma dicing delivers in relation to the quality and reliability
Publikováno v:
Optics Communications. 265:120-125
In this paper, we demonstrate mitigation of pattern-induced degradation in an optical crosspoint switch (OXS) matrix by utilizing differential phase shift keying (DPSK) modulation format. We experimentally demonstrate 4 × 4 unicast optical packet sw
Publikováno v:
2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS).
Endpoint detection (EPD) is a critical control functionality for many etch processes, especially for deep silicon etches [1] that terminate on an underlayer. Where this device structure is employed, it is vital that the point at which the etch proces
Autor:
Mark Carruthers, Oliver Ansell, Hefin Griffiths, Keith Buchanan, Kath Crook, Dave Thomas, Dan Archard
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ∼200:1 can be achieved on bonded