Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Okko Jarvinen"'
Autor:
Okko Jarvinen, Vishnu Unnikrishnan, Waqas Siddiqui, Teuvo Korhonen, Kimmo Koli, Kari Stadius, Marko Kosunen, Jussi Ryynanen
Publikováno v:
IEEE Access, Vol 9, Pp 48147-48156 (2021)
This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantizat
Externí odkaz:
https://doaj.org/article/c3a5a1ab605a442c95eb58dad7aea1da
Autor:
Okko Jarvinen, Vishnu Unnikrishnan, Ilia Kempi, Santeri Porrasmaa, Kari Stadius, Marko Kosunen, Jussi Ryynanen
This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied to implement a cyclic-coupled ring oscillator (CCRO). Compared to an inverter-based CC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::38d6ef367ae059995c941b7e788ab431
https://aaltodoc.aalto.fi/handle/123456789/116872
https://aaltodoc.aalto.fi/handle/123456789/116872
Autor:
Kari Stadius, Okko Jarvinen, Waqas Siddiqui, Jussi Ryynanen, Marko Kosunen, Vishnu Unnikrishnan
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:203-214
An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::322d882dec46abc0934815d14a41d170
https://doi.org/10.1109/tvlsi.2020.3031028
https://doi.org/10.1109/tvlsi.2020.3031028
Autor:
Vishnu Unnikrishnan, Waqas Siddiqui, Marko Kosunen, Okko Jarvinen, Teuvo Korhonen, Kimmo Koli, Jussi Ryynanen, Kari Stadius
Publikováno v:
IEEE Access. 9:48147-48156
This paper presents the first measured cyclic-coupled ring oscillator (CCRO) time-to-digital converter (TDC). The CCRO realizes a robust true time-domain delay interpolation with sub-gate-delay resolution. The architecture employs real-time quantizat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::110a8be6e5bf4160825fc7f333f4a171
https://doi.org/10.1109/access.2021.3068838
https://doi.org/10.1109/access.2021.3068838
Publikováno v:
2022 IEEE International Symposium on Circuits and Systems (ISCAS).
Publisher Copyright: © 2022 IEEE. Cyclic-coupled ring oscillators (CCRO), which consist of M ring oscillators each with N inverting stages, can be used in time-domain data converters to achieve sub-gate-delay resolution and improved phase noise perf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::11d7728da3f2fca1636c7c0dd3fd341b
https://doi.org/10.1109/iscas48785.2022.9937816
https://doi.org/10.1109/iscas48785.2022.9937816
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a8ea9d913de324271ffc3d76e3022bc6
https://aaltodoc.aalto.fi/handle/123456789/113050
https://aaltodoc.aalto.fi/handle/123456789/113050
Publisher Copyright: © 2022 IEEE. Time-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::beec13f549d90336feb9914a1214c1ed
https://aaltodoc.aalto.fi/handle/123456789/118661
https://aaltodoc.aalto.fi/handle/123456789/118661
Publikováno v:
Scopus-Elsevier
ISCAS
ISCAS
A digital-friendly approach to implement injection-locked ring oscillators is proposed. We show that lock can be achieved by dynamically switching the delay of a delay element in a ring oscillator. A logic gate that generates the control signal for s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::47989c1a908ba3305ad14794b8176fd7
http://www.scopus.com/inward/record.url?eid=2-s2.0-85109330316&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-85109330316&partnerID=MN8TOARS
Autor:
Jarvinen, Okko, Unnikrishnan, Vishnu, Kempi, Ilia, Porrasmaa, Santeri, Stadius, Kari, Kosunen, Marko, Ryynanen, Jussi
Publikováno v:
IEEE Transactions on Circuits & Systems. Part II: Express Briefs; Sep2022, Vol. 69 Issue 9, p3709-3713, 5p