Zobrazeno 1 - 10
of 112
pro vyhledávání: '"Okihiko Ishizuka"'
Publikováno v:
IEICE Transactions on Information and Systems. :2073-2079
In this paper, optimization and verification of the current-mode multiple-valued digit ORNS arithmetic circuits are presented. The multiple-valued digit ORNS is the redundant number system using digit values in the multiple-valued logic and it realiz
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1622-1625
In this letter, two kinds of MOS operational transconductance amplifiers (OTAs) based on combiners are presented. Each OTA has the following advantages; one of the proposed OTAs (OTA-1) can be operated at low supply voltage and the other OTA (OTA-2)
Publikováno v:
IEEJ Transactions on Electronics, Information and Systems. 123:1101-1108
The problem under consideration centers on building a three-dimensional description of the unprepared environment of an autonomous mobile robot. In an image sequence, tracking is to be performed after image rectification. This intermediate process mi
Publikováno v:
Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 84:28-40
In this paper, we propose a hill-climbing learning method for Hopfield networks in which the energy of the network is intentionally raised in the weight space so that the network can escape from local minima. This learning method involves repeated up
Publikováno v:
Systems and Computers in Japan. 32:31-41
In this paper the authors propose an immune network which considers B cell interactions based on the immune response network of an organism. The authors modeled a network based on an immune mechanism which uses B cell interactions for an immune respo
Publikováno v:
Electronics and Communications in Japan (Part III: Fundamental Electronic Science). 84:11-24
In this paper, a model of the neuron based on the dendrite mechanism is proposed. The neuron model takes the form of a dendrite, and the interaction between synapses and so on, which are not considered by the conventional model, is taken into account
Publikováno v:
IEEJ Transactions on Electronics, Information and Systems. 121:1747-1754
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47:473-477
In this work, we present a four-quadrant CMOS current-mode multiplier based on the square-law characteristics of an MOS transistor operated in the saturation region. One advantage of this multiplier is that the output current is independent of MOS tr
Publikováno v:
IEEJ Transactions on Electronics, Information and Systems. 120:1012-1019
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46:172-177
In this paper, a novel CMOS voltage follower with resistive-load drivability is proposed. The proposed follower consists of only three MOS transistors and one current mirror. The output voltage of the circuit is insensitive to MOS transistor device p