Zobrazeno 1 - 10
of 64
pro vyhledávání: '"Oana Boncalo"'
Autor:
Marian-Emanuel Ionascu, Nuria Castell, Oana Boncalo, Philipp Schneider, Marius Darie, Marius Marcu
Publikováno v:
Sensors, Vol 21, Iss 23, p 7977 (2021)
During the last decade, extensive research has been carried out on the subject of low-cost sensor platforms for air quality monitoring. A key aspect when deploying such systems is the quality of the measured data. Calibration is especially important
Externí odkaz:
https://doaj.org/article/b14f91532ee744dda0ceec5eb5e27c14
Autor:
Philipp Schneider, Marius Darie, Oana Boncalo, Nuria Castell, Marius Marcu, Marian-Emanuel Ionascu
Publikováno v:
Sensors (Basel, Switzerland)
Sensors
Sensors; Volume 21; Issue 23; Pages: 7977
Sensors, Vol 21, Iss 7977, p 7977 (2021)
Sensors
Sensors; Volume 21; Issue 23; Pages: 7977
Sensors, Vol 21, Iss 7977, p 7977 (2021)
During the last decade, extensive research has been carried out on the subject of low-cost sensor platforms for air quality monitoring. A key aspect when deploying such systems is the quality of the measured data. Calibration is especially important
Publikováno v:
2020 28th Telecommunications Forum (TELFOR).
Unrolled layered LDPC architectures have been shown to obtain tens of Gbps throughputs. These types of decoders are well suited to array LDPC codes, for which they present improved throughput. In this paper, we propose a generalization for unrolled l
Autor:
Alexandru Amaricai, Oana Boncalo
Publikováno v:
SACI
This paper discusses the problems of message map-ping and message access scheduling for data hazards avoidance in layered Low-Density Parity-Check Decoder architectures, by using in-order message update strategy. We provide a detailed description of
Publikováno v:
Microprocessors and Microsystems. 63:216-225
This paper presents an architecture-aware Progressive Edge Growth (PEG)-based construction method for Low-Density Parity-Check (LDPC) codes. We target optimization through code construction for layered architectures with pipelined processing and memo
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2017, pp.1-13. ⟨10.1109/TCSI.2017.2777802⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, pp.1-13. ⟨10.1109/TCSI.2017.2777802⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2017, pp.1-13. ⟨10.1109/TCSI.2017.2777802⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, pp.1-13. ⟨10.1109/TCSI.2017.2777802⟩
Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers a significant improvement in error correction, approaching the performance of soft-information decoders on the bina
Publikováno v:
IEEE Communications Letters
IEEE Communications Letters, Institute of Electrical and Electronics Engineers, 2018, 22 (1), pp.13-16. ⟨10.1109/LCOMM.2017.2718523⟩
IEEE Communications Letters, Institute of Electrical and Electronics Engineers, 2018, 22 (1), pp.13-16. ⟨10.1109/LCOMM.2017.2718523⟩
In this letter, we address the issue of early stopping criterion for layered LDPC decoders, aiming at more safeness with low hardware cost and minimum latency. We introduce a new on-the-fly measure in the decoder, called in-between layers partial syn
Publikováno v:
DSD
In this paper, we present a parametric hardware accelerator for Takagi-Sugeno fuzzy controllers. The architecture consists of an application specific weighting function computation block, generic control output computation unit, and a programmable re
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩
IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66 (4), pp.1643-1656. ⟨10.1109/TCSI.2018.2884252⟩
International audience; This paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture usi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2edd576b5f2bce23e84d7edb175f769
https://hal-cea.archives-ouvertes.fr/cea-02186481
https://hal-cea.archives-ouvertes.fr/cea-02186481
Publikováno v:
Advances in Electrical and Computer Engineering, Vol 16, Iss 1, Pp 93-98 (2016)
This paper proposes data-dependent reliability evaluation methodology for digital systems described at Register Transfer Level (RTL). It uses a hybrid hierarchical approach, combining the accuracy provided by Gate Level (GL) Simulated Fault Injection