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Workload-dependent BTI analysis in a processor core at high level

Autor: S. Mbarek, E. Piriou, Vincent Huard, C. Sandionigi, O. Heron

Publikováno v: IEEE International Reliability Physics Symposium Proceedings
IEEE International Reliability Physics Symposium Proceedings, Apr 2015, Monterrey, United States. pp.CA61--CA66, ⟨10.1109/IRPS.2015.7112784⟩
IRPS

International audience; This work presents a software tool that enables joint architecture simulation and estimation of ageing-induced timing drifts at register-transfer level (RTL). The objective is to enable design exploration of processor microarc

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc7a471e58f4d7c5ba934c89be58a7cb
https://cea.hal.science/cea-01719961

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RAAPS: Reliability Aware ArchC based Processor Simulator

Autor: O. Heron, François Marc, N. Ventroux, C. Bertolini, Thomas Zimmer, Tushar Gupta

Publikováno v: 2010 IEEE International Integrated Reliability Workshop Final Report.

In semiconductor industry, designing a SoC is a complex process. Designing reliable SoCs includes study of various configurations involving different operating conditions and considering both hard and soft errors. Designers at higher level of abstrac

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8fc1719cb6db7687fe5a9d3ff1472494
https://doi.org/10.1109/iirw.2010.5706512

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Effects of various applications on relative lifetime of processor cores

Autor: Thomas Zimmer, N. Ventroux, O. Heron, Tushar Gupta, François Marc, C. Bertolini

Publikováno v: Proceedings of International Integrated Reliability Workshop 2009
International Integrated Reliability Workshop
International Integrated Reliability Workshop, Oct 2009, South Lake Tahoe, United States
Proc. of IRW
IRW
IRW, Oct 2009, Lake Tahoe, United States. pp.1

The lifetime of integrated chip tends to decrease more and more with technology scaling. To check if a design is robust, in this paper we present RTME (Real Time MTTF Evaluation), a simulation framework that enables the evaluation of Reliability at h

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::237834fb2773842361cc79ea135f2050
https://hal.science/hal-00499480

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On the reliability evaluation of sram-based FPGA designs

Autor: O. Heron, T. Arnaout, Hans-Joachim Wunderlich

Publikováno v: FPL

Benefits of field programmable gate arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to so

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9d7e1beeeac816d72115b719a3009053
https://doi.org/10.1109/fpl.2005.1515755

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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

Autor: P. Girard, O. Heron, S. Pravossoudovitch, M. Renovell

Publikováno v: Testing and Robust System Design
IOLTS: International
Testing Symposium
Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.187-192, ⟨10.1109/OLT.2004.1319686⟩

International audience; In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::832020b371bde190baf05be9e07ae66f
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108824/document

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