Zobrazeno 1 - 10
of 87
pro vyhledávání: '"O. Fursenko"'
Akademický článek
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Autor:
A. Kruger, Jürgen Drews, D. Stolarek, Julia Kitzmann, Jarek Dabrowski, F. Coccetti, K. Schulz, Jens Katzer, Sebastian Schulze, P. Kulse, Mirko Fraschke, O. Fursenko, André Wolff, M. Lukosius, M. Lisker, A.M. Schubert, G. Dziallas, Ioan Costina, Andreas Mai, D. Wolansky
Publikováno v:
Microelectronic Engineering. 205:44-52
We present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200 mm wafer pilot line routinely used for the fabrication of integrated circuits in Si technologies. We demonstrate key process steps and discuss
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eef682f720e5ce3461de341d73abd802
https://doi.org/10.1016/j.mee.2018.11.007
https://doi.org/10.1016/j.mee.2018.11.007
Autor:
Matthias Wietstruck, O. Fursenko, Rasuole Lukose, Yuji Yamamoto, Mehmet Kaynak, Patrick Kruger, Thomas Voss, A. Kruger, M. Lisker
Publikováno v:
2020 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP).
In this work, transfer of the Ge layer on to a SiO2 layer to realize a Ge-on-Insulator (GOI) wafer is performed based on a wafer-level bonding process. The process flow starts with the preparation of the target (Si wafer with SiO2) and the donor (Si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::738568a9b66d13c7412b5a94ed4cee45
https://doi.org/10.1109/dtip51112.2020.9139149
https://doi.org/10.1109/dtip51112.2020.9139149
Autor:
N. O. Fursenko
Publikováno v:
World of Economics and Management. 18:126-139
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::981de887fb315b48c8ce1fc54403e1dd
https://doi.org/10.25205/2542-0429-2018-18-3-126-139
https://doi.org/10.25205/2542-0429-2018-18-3-126-139
Autor:
G. Lupina, Thomas Schroeder, P. Kulse, Yuji Yamamoto, O. Fursenko, Andreas Trusch, Andre Wolff, Ioan Costina, M. Lisker, M. Lukosius, Andreas Mai, Gunther Lippert, Julia Kitzmann, A. Kruger, J. Dabrowski
Publikováno v:
ECS Transactions. 75:533-540
Graphene is considered as a material which can enable new functionalities and performance improvements in a large variety of applications, among them in microelectronics [1, 2]. In microelectronics, techniques required for commercial large scale fabr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d8497eeec132654cac102c0d9f7734f0
https://doi.org/10.1149/07508.0533ecst
https://doi.org/10.1149/07508.0533ecst
Publikováno v:
Microelectronic Engineering. 139:70-75
Display Omitted 3D metrology of deeply-etched structures with an aspect ratio of more than 10.Estimation position and size (amplitude and period) of scallops on the side wall.Monitoring realized by spectroscopic reflectometry using wafer metrology to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16ff7697b8002dc6be353059a20bdf45
https://doi.org/10.1016/j.mee.2015.04.121
https://doi.org/10.1016/j.mee.2015.04.121
Akademický článek
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Autor:
Sigurd Schrader, Andreas Mai, Friedhelm Heinrich, Joachim Bauer, Patrick Steglich, O. Fursenko, Silvio Pulwer, Claus Villringer, Steffen Marschmeyer, A. Bluemich
Through Silicon Via (TSV) technology is a key feature of new 3D integration of circuits by creation of interconnections using vias, which go through the silicon wafer. Typically, the highly-selective Bosch Si etch process, characterized by a high etc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8b0b6ff7ee7fef8153c99890c8671702
https://opus4.kobv.de/opus4-th-wildau/frontdoor/index/index/docId/1375
https://opus4.kobv.de/opus4-th-wildau/frontdoor/index/index/docId/1375
Autor:
Yuji Yamamoto, Julia Kitzmann, Sebastian Schulze, Gunther Lippert, Andreas Mai, Grzegorz Lupina, Mindaugas Lukosius, H. M. Krause, Fatima Akhtar, Thomas Schroeder, Marco Lisker, André Wolff, O. Fursenko, M. A. Schubert, Jarek Dabrowski
Publikováno v:
ACS applied materialsinterfaces. 8(49)
Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH4 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ca9ce17e806574f544e267c03e65fbc
https://pubmed.ncbi.nlm.nih.gov/27960421
https://pubmed.ncbi.nlm.nih.gov/27960421
Autor:
Steffen Marschmeyer, J. Schmidt, A. Scheit, P. Kulse, Holger Rucker, D. Wolansky, J. Drews, Gunter Fischer, T. Lenke, O. Fursenko, Frank Herzel, Jens Katzer, A. Fox, C. Wipf, Thomas Grabolla, F. Barwolf, Marco Lisker, D. Schmidt, M. A. Schubert, Andreas Trusch, R. Barth, A. Kruger, J. Korn, Bernd Heinemann
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a676cf9bca9456614fa4639e694c6da3
https://doi.org/10.1109/iedm.2016.7838335
https://doi.org/10.1109/iedm.2016.7838335