Zobrazeno 1 - 10
of 190
pro vyhledávání: '"Nur A. Touba"'
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-c
Publikováno v:
IEEE Transactions on Computers. 71:992-1007
Phase Change Memory (PCM), with its better scaling potential compared to DRAM, is seen as a promising candidate to replace or complement DRAM. The heat generated from a RESET programming pulse to a PCM cell can disturb the neighboring cells which are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88df20ff36d3cdc045c44b4277bd5d5b
https://doi.org/10.1109/tc.2021.3068577
https://doi.org/10.1109/tc.2021.3068577
Autor:
Abhishek Das, Nur A. Touba
Publikováno v:
IEEE Transactions on Computers. 69:253-259
With technology scaling, burst errors or clustered errors are becoming increasingly common in different types of memories. Multiple bit upsets due to particle strikes, write disturbance errors, and magnetic field coupling are a few of the mechanisms
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be477127b0027f9a23c5df9550d42f85
https://doi.org/10.1109/tc.2019.2947425
https://doi.org/10.1109/tc.2019.2947425
Autor:
Abhishek Das, Nur A. Touba
Publikováno v:
IEEE Transactions on Nanotechnology. 18:575-583
As technology scales further, dynamic random-access memory (DRAM) scaling faces numerous challenges. Emerging non-volatile main memories (e.g., phase change memories) provide an attractive solution to the challenges faced by DRAM scaling due to their
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6292ffaa2248a293de570e4c65f554a
https://doi.org/10.1109/tnano.2019.2917139
https://doi.org/10.1109/tnano.2019.2917139
Autor:
Nur A. Touba, Abhishek Das
Publikováno v:
VTS
Resistive RAM technology with it’s in memory computation and matrix vector multiplication capabilities has paved the way for efficient hardware implementations of neural networks. The ability to store the training weights and perform a direct matri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d10964f9bb645996c46cda63812df9c0
https://doi.org/10.1109/vts48691.2020.9107606
https://doi.org/10.1109/vts48691.2020.9107606
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1580-1591
Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::889b05434457456ec694a66a7ec82930
https://doi.org/10.1109/tcad.2017.2682639
https://doi.org/10.1109/tcad.2017.2682639
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1571-1579
Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5aade70e48604930cd0f085037c4827c
https://doi.org/10.1109/tcad.2017.2681063
https://doi.org/10.1109/tcad.2017.2681063
Autor:
Nur A. Touba, Abhishek Das
Publikováno v:
VTS
As memory technology scales, the demand for higher performance and reliable operation is increasing as well. For main memory, e.g., DRAM, a conventional single error correcting double error detecting (SEC-DED) code may not be sufficient. However, exi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62c93f449337a8cac91abb5f4bd0e217
https://doi.org/10.1109/vts.2019.8758647
https://doi.org/10.1109/vts.2019.8758647
Autor:
Nur A. Touba, Abhishek Das
Publikováno v:
VTS
The IEEE Std. 1687 (IJTAG) was designed to provide on-chip access to the various embedded instruments (e.g. built-in self test, sensors, etc.) in complex system-on-chip designs. IJTAG facilitates access to on-chip instruments from third party intelle
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3876b4122663c4863015e23948111984
https://doi.org/10.1109/vts.2019.8758608
https://doi.org/10.1109/vts.2019.8758608
Autor:
Abhishek Das, Nur A. Touba
Publikováno v:
LATS
The number of marginal cells in static random-access memory (SRAM) increases as technology scales further. Spin transfer torque magnetic random-access memory (STT-MRAM) which is gaining popularity as a L3 cache alternative due to their small size, no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55c3c730ab90a432c4ac9f0b6589e7c2
https://doi.org/10.1109/latw.2019.8704568
https://doi.org/10.1109/latw.2019.8704568