Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Nun-Sian Tsai"'
Autor:
Nun-Sian Tsai, Tong-Sen Chang, Hung-Ming Chuang, Kuo-Hwa Lee, Sheng-Fu Tsai, Hsin-Chien Lin, Kong-Beng Thei, Chung-Long Cheng, Wen-Chau Liu
Publikováno v:
IEEE Transactions on Electron Devices. 50:516-518
A new and improved structure of polysilicon resistor for subquarter micrometer CMOS device applications has been demonstrated and studied. A simple model is proposed to analyze its important parameters such as the voltage-dependent bulk sheet resista
Cavity-down thermal-enhanced package reliability evaluation for low-k dielectric/Cu interconnects IC
Publikováno v:
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).
It has been well recognized that IC packaging materials have a great impact on the IC chip integrity of chips fabricated by low dielectric constant inter-metal-dielectric (Low-k IMD) materials. To understand the effect of the package process and mate
Publikováno v:
2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).
Due to low dielectric constant inter-metal-dielectric (low-k IMD) materials possessing weaker mechanical properties and higher coefficient of thermal expansion (CTE) compared with IC silicon substrates, the integrity of advanced IC low-k IMD layer/si
Publikováno v:
Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.
A novel analytic model for minority-carrier well-type guard ring design has been developed for CMOS circuits. This model, expressed as a function of epi-layer thickness, well junction depth, and guard ring width, has been verified by two-dimensional
Publikováno v:
Proceedings of the 1991 International Conference on Microelectronic Test Structures.
The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown ex
Autor:
Nun-Sian Tsai
Publikováno v:
Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).
Five pilot or production Fabs were set up in the year 2000 to start 300 mm integration wafers. TSMC was one of them and had started a pilot production line in Fab 6, Tainan, Taiwan. After 300 mm tool installation in 3Q/00, TSMC had successfully compl
Publikováno v:
Proceedings of the 1991 International Conference on Microelectronic Test Structures; 1990, p231-235, 5p
Publikováno v:
2004 Proceedings 54th Electronic Components & Technology Conference (IEEE Cat. No.04CH37546); 2004, p1191-1191, 1p
Publikováno v:
2004 Proceedings 54th Electronic Components & Technology Conference (IEEE Cat. No.04CH37546); 2004, p767-767, 1p
Publikováno v:
Proceedings of the IEEE 1991 Custom Integrated Circuits Conference; 1991, p4.5/1-4.5/4, 1p