Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Norio Shoji"'
Autor:
Zhiwei Zhou, Jeremy Chatwin, Ryota Shinoda, Ueno Yosuke, Koki Uchino, Jacob Adams Wysocki, Hideyuki Suzuki, Norio Shoji, Masuda Takashi, Kenichi Maruko, Yoshifumi Miyajima
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:3204-3215
A wide band, low power, injection-locked oscillator (ILO)-type clock and data recovery (CDR) with high jitter tolerance is implemented in 28 nm CMOS. A robust phase and frequency detection algorithm independently controls ILO free running frequency a
Autor:
Iida Sachio, Norihito Suzuki, Ken Yamamoto, Masahisa Tamura, Aoki Hiroshi, Norio Shoji, Seiji Kobayashi, Naoto Yoshikawa, Tanaka Katsuyuki, Noboru Sasho, Hideshi Motoyama
Publikováno v:
2018 48th European Microwave Conference (EuMC).
A sub-GHz transmitter which has a constant envelope $\pi/2$ shift BPSK modulator is described. To realize constant envelope and low EVM, we have designed that the modulator is composed of a specially designed root raised cosine filter ( $\alpha=0.65$
Autor:
Harada Shingo, Mari Kishikawa, Gaku Hidai, Hitoshi Tomiyama, Nobuhisa Ozawa, Masayuki Katakura, Yuya Kondo, Hideyuki Takano, Norio Shoji, Hiroyasu Tagami, Daisuke Ide, Hidenori Takeuchi, Shinichiro Eto, Kenichi Nakano, Yusuke Shinohe, Kondo Fumitaka, Ken Yamamoto
Publikováno v:
ISSCC
We are approaching the age of IoE, in which wearable devices such as smart watches will be widespread. Sensing processors play a key role and the Global Navigation Satellite System (GNSS) is considered fundamental. Power consumption is one of the mos
Autor:
Ueno Yosuke, Hideyuki Suzuki, Norio Shoji, Hideyuki Matsumoto, Zhiwei Zhou, Masuda Takashi, Jeremy Chatwin, Jacob Adams Wysocki, Kenichi Maruko, Koki Uchino, Yoshifumi Miyajima, Ryota Shinoda
Publikováno v:
ISSCC
The consumer electronics market demands high-speed and low-power serial data interfaces. The injection locked oscillator (ILO) based clock and data recovery (CDR) circuit [1–2], is a well-known solution for these demands. The typical solution has a
Publikováno v:
Zairyo-to-Kankyo. 41:89-95
Autor:
K. Takeshita, T. Mogi, H. Iizuka, Jeremy Chatwin, A. Igarashi, D. Mellor, I. Butler, Hideyuki Suzuki, Masuda Takashi, Norio Shoji
Publikováno v:
ISSCC
A full-rate 10 Gb/s transceiver core employing a tri-state binary PD with 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered
Autor:
B. Griffiths, K. Tanaka, I. Butler, Norio Shoji, Jeremy Chatwin, D. Mellor, S. Iida, F. Hayden, N. Yoshikawa, Hideyuki Suzuki
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A DSSS UWB transceiver using the 3.1 to 5 GHz band is implemented in 0.18 /spl mu/m CMOS and includes a programmable pulse shaping circuit in the transmitter, an LNA with a NF of 4 dB and a 6/sup th/-order active LPF with a bandwidth of 500 MHz in th
Periodical
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