Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Nori, Anant V."'
Autor:
Bera, Rahul, Ranganathan, Adithya, Rakshit, Joydeep, Mahto, Sujit, Nori, Anant V., Gaur, Jayesh, Olgun, Ataberk, Kanellopoulos, Konstantinos, Sadrosadati, Mohammad, Subramoney, Sreenivas, Mutlu, Onur
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predi
Externí odkaz:
http://arxiv.org/abs/2406.18786
Data Prefetching is a technique that can hide memory latency by fetching data before it is needed by a program. Prefetching relies on accurate memory access prediction, to which task machine learning based methods are increasingly applied. Unlike pre
Externí odkaz:
http://arxiv.org/abs/2205.14778
Machine learning algorithms have shown potential to improve prefetching performance by accurately predicting future memory accesses. Existing approaches are based on the modeling of text prediction, considering prefetching as a classification problem
Externí odkaz:
http://arxiv.org/abs/2205.02269
Autor:
Bera, Rahul, Kanellopoulos, Konstantinos, Nori, Anant V., Shahroodi, Taha, Subramoney, Sreenivas, Mutlu, Onur
Past research has proposed numerous hardware prefetching techniques, most of which rely on exploiting one specific type of program context information (e.g., program counter, cacheline address) to predict future memory accesses. These techniques eith
Externí odkaz:
http://arxiv.org/abs/2109.12021
Autor:
Nori, Anant V., Bera, Rahul, Balachandran, Shankar, Rakshit, Joydeep, Omer, Om J., Abuhatzera, Avishaii, Kuttanna, Belliappa, Subramoney, Sreenivas
Deep Neural Network (DNN) inference is emerging as the fundamental bedrock for a multitude of utilities and services. CPUs continue to scale up their raw compute capabilities for DNN inference along with mature high performance libraries to extract o
Externí odkaz:
http://arxiv.org/abs/2011.11695
High main memory latency continues to limit performance of modern high-performance out-of-order cores. While DRAM latency has remained nearly the same over many generations, DRAM bandwidth has grown significantly due to higher frequencies, newer arch
Externí odkaz:
http://arxiv.org/abs/1910.03075