Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Nooshin Nosrati"'
Autor:
Nooshin Nosrati, Zainalabedin Navabi
Publikováno v:
IEEE Access, Vol 12, Pp 52851-52866 (2024)
As Long Short-Term Memory (LSTM) accelerators are increasingly being employed in safety-critical applications with high-reliability demands, protecting them against errors becomes imperative. Traditional protection techniques for LSTMs are either cos
Externí odkaz:
https://doaj.org/article/24a94d1de94b496288aa32e81b44bbeb
Publikováno v:
2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::468f9828783e8eb4e7cfdf85e2507715
https://doi.org/10.1109/iolts56730.2022.9897309
https://doi.org/10.1109/iolts56730.2022.9897309
Publikováno v:
2022 IEEE European Test Symposium (ETS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfea5333395f3d9b1e48f6f4f3ea4c8e
https://doi.org/10.1109/ets54262.2022.9810369
https://doi.org/10.1109/ets54262.2022.9810369
Autor:
Zahra Mahdavi, Nooshin Nosrati, Zainalabedin Navabi, Katayoon Basharkhah, Hanieh Totonchi Asl
Publikováno v:
DTIS
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::54d9650ac859f9795a9987fabee41b90
https://doi.org/10.1109/dtis53253.2021.9505110
https://doi.org/10.1109/dtis53253.2021.9505110
Publikováno v:
2020 10th International Conference on Computer and Knowledge Engineering (ICCKE).
With deep submicron scaling and integrating multi and many cores on a single chip, Network-on-Chip (NoC) has been proposed as a scalable and cost-effective solution for inter-core communication. Data exchange between cores does not follow a uniform t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4dc7668574576d0c355adf62940d212
https://doi.org/10.1109/iccke50421.2020.9303650
https://doi.org/10.1109/iccke50421.2020.9303650
Autor:
Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Seyedeh Maryam Ghasemi, Zainalabedin Navabi, Maryam Rajabalipanah
Publikováno v:
DDECS
The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and machine learning. The accelerato
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b72fc4c036113cabf7ef1046a411ce39
https://doi.org/10.1109/ddecs50862.2020.9095688
https://doi.org/10.1109/ddecs50862.2020.9095688
Publikováno v:
VTS
At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for cores connecting to each other to estimate, and thus model, crosstalk noise res
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22e086ac9ecbceaa9f41a3b160ead4c9
https://doi.org/10.1109/vts48691.2020.9107612
https://doi.org/10.1109/vts48691.2020.9107612
Autor:
Zainalabedin Navabi, Seyedeh Maryam Ghasemi, Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Maryam Rajabalipanah
Publikováno v:
DFT
Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19d74d3e7e4b565f80ff9ffee315293c
https://doi.org/10.1109/dft50435.2020.9250763
https://doi.org/10.1109/dft50435.2020.9250763
Autor:
Jaan Raik, Zainalabedin Navabi, Rezgar Sadeghi, Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Maksim Jenihhin
Publikováno v:
EWDTS
Hardware implementation of many of today's applications such as those in automotive, telecommunication, bio, and security, require heavy repeated computations, and concurrency in the execution of these computations. These requirements are not easily
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e5d73450b1f58e1409ccb2e222505a6e
https://doi.org/10.1109/ewdts.2019.8884481
https://doi.org/10.1109/ewdts.2019.8884481
Autor:
Katayoon Basharkhah, Christoph Grimm, Nooshin Nosrati, Zainalabedin Navabi, Rezgar Sadeghi, Carna Zivkovic
Publikováno v:
EWDTS
Nowadays electronic systems are moving toward more complex designs with various computation and communication blocks. In addition to test requirements for individual system blocks, the functionality of the overall system must also be tested. Conventi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9980468b8b12882fff6edc9558751ae7
https://doi.org/10.1109/ewdts.2019.8884423
https://doi.org/10.1109/ewdts.2019.8884423