Výsledky vyhledávání - "Nobutaro Shibata"

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

Autor: Yoshinori Gotoh, Nobutaro Shibata

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1415-1428

A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI desig

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ad1136e5eab9b3ea5d57804e05890b53
https://doi.org/10.1109/tvlsi.2014.2341352

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An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi- $\mathrm{V}_{\rm DD}$ CMOS/SIMOX Techniques

Autor: Mika Nishisaka, Yasuhiro Sato, Nobutaro Shibata, Yusuke Ohtomo

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1089-1102

Many of the current wireline networks are digitalized. In Japan, a synchronous digital hierarchy (SDH) system is installed in the public switched telephone network, and application data are transferred with a synchronous transfer module (STM). This p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::97b253ad063210ba6736d05ee1c2d680
https://doi.org/10.1109/tvlsi.2014.2333589

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Signal-to-Noise Ratio Analysis of a Noisy-Channel Model for a Capacitively Coupled Personal Area Network

Autor: Hiroki Morimura, Mitsuru Shinagawa, Ai-ichiro Sasaki, Nobutaro Shibata, Ryusuke Kawano, Takako Ishihara

Publikováno v: IEEE Transactions on Antennas and Propagation. 61:390-402

We investigated a noisy-channel model for a capacitively coupled personal area network (CC-PAN) with megahertz-frequency signals. The new channel model describes the influence of a power line connected to transceivers. Using the model, we analyzed ch

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a921b71a07a639caa114e7353fc06c07
https://doi.org/10.1109/tap.2012.2220110

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A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells

Autor: Nobutaro Shibata, Mayumi Watanabe, Hideomi Okiyama

Publikováno v: IEEE Journal of Solid-State Circuits. 45:1856-1869

The use of multiple power supplies with different output voltages has a great advantage in that it makes it possible to realize high performance ULSIs with low power dissipation. This paper presents a high-speed low-power SRAM that employs three powe

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::98fe96bd3e1d0ed8d91ec42060b89ca7
https://doi.org/10.1109/jssc.2010.2051262

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A 0.5-V 25-MHz 1-mW 256-Kb MTCMOS/SOI SRAM for Solar-Power-Operated Portable Personal Digital Equipment—Sure Write Operation by Using Step-Down Negatively Overdriven Bitline Scheme

Autor: H. Kiya, S. Kurita, H. Okamoto, Nobutaro Shibata, M. Tan'no, T. Douseki

Publikováno v: IEEE Journal of Solid-State Circuits. 41:728-742

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power sw

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8734254318d9a5e65502acad83815f08
https://doi.org/10.1109/jssc.2005.864124

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A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation

Autor: Toshishige Shimamura, Nobutaro Shibata, Takakuni Douseki

Publikováno v: IEICE Transactions on Electronics. :582-588

This paper describes a speed-oriented ullralow-voltage and low-power SOI circuit technique based on a differential enhancementand depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-V th CMOS circuit bloc

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fcf1465280e1d8c3c10a717745973e6c
https://doi.org/10.1093/ietele/e88-c.4.582

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