Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Nobuo Tamba"'
Autor:
Shinji Tanaka, Shigeto Yoshida, Kazufumi Kaneda, Masayuki Odagawa, Tetsushi Koide, Masayuki Tsuji, Nobuo Tamba, Toru Tamaki, Takumi Okamoto, Takayuki Sugawara, Hiroshi Toishi, Hiroshi Mieno, Bisser Raytchev
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :691-701
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12320c42755063d71bd1b731e9945c2d
https://doi.org/10.1587/transfun.2020eap1069
https://doi.org/10.1587/transfun.2020eap1069
Autor:
Hiroshi Mieno, Kazufumi Kaneda, Masayuki Odagawa, Toru Tamaki, Shigeto Yoshida, Shinji Tanaka, Bisser Raytchev, Masayuki Tsuji, Hiroshi Toishi, Tetsushi Koide, Takumi Okamoto, Takayuki Sugawara, Nobuo Tamba
Publikováno v:
ISCAS
This paper presents a hardware implementation of a computer-aided diagnosis system that can classify lesions in real time for endoscopic video image. Unlike still images, video images contain many color shifts, blurs, reflections, and so on, a classi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20760543ef6424dcd833d72157a9e7b1
https://doi.org/10.1109/iscas.2019.8702379
https://doi.org/10.1109/iscas.2019.8702379
Autor:
Toru Tamaki, Shigeto Yoshida, Shinji Tanaka, Nobuo Tamba, Tetsushi Koide, Takumi Okamoto, Takayuki Sugawara, Hiroshi Mieno, Masayuki Tsuji, Hiroshi Toishi, Bisser Raytchev, Kazufumi Kaneda, Masayuki Odagawa
Publikováno v:
TENCON
In this paper, the computer-aided diagnosis system for colorectal endoscopic images is proposed. The proposed system is consisted of Convolutional Neural Network (CNN) as the feature extraction processing and Support Vector Machine (SVM) as identific
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8370d36fe7069ce5989cc0e5d7bfdf2e
https://doi.org/10.1109/tencon.2018.8650331
https://doi.org/10.1109/tencon.2018.8650331
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%
Autor:
H. Miki, Yuji Yokoyama, S. Miyaoka, T. Ueda, M. Kaneda, E. Yamasaki, M. Yagyu, Nobuo Tamba, M. Hasegawa, M. Todokoro, H. Akasaki, K. Toriyama, M. Katayama, T. Kobayashi, Y. Tanaka, K. Takashima, N. Itoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:503-509
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f86c5259fcbb8deb8d558d10bd05b56f
https://doi.org/10.1109/4.910489
https://doi.org/10.1109/4.910489
Autor:
T. Ikeda, T. Igarashi, Akihisa Uchida, Masanori Odaka, S. Ohmori, K. Watanabe, H. Hayashi, T. Muraya, Toshiro Hiramoto, Masayuki Ohayashi, Kunihiko Yamaguchi, S. Tsuji, Hiroaki Nambu, M. Yoshida, Kazuhiro Akimoto, T. Kokubu, A. Kishimoto, T. Fujiwara, A. Anzai, N. Handa, Nobuo Tamba
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:1344-1352
A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. Th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::caccec2359e983e221789fec41f5abab
https://doi.org/10.1109/4.328635
https://doi.org/10.1109/4.328635
Autor:
Yoshiaki Sakurai, K. Watanabe, Noriyuki Homma, Kenichi Ohhata, T. Ikeda, Nobuo Tamba, Hiroaki Nambu, Toshiro Hiramoto, Kazuo Kanetani, Youji Idei, Masanori Odaka, Kunihiko Yamaguchi
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:632-640
Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6cc2cd5d34b7aede04963acc1671503
https://doi.org/10.1109/4.126554
https://doi.org/10.1109/4.126554
Autor:
Kenichi Ohhata, T. Ikeda, Noriyuki Homma, Hiroaki Nambu, Youji Idei, Toshiro Hiramoto, Kunihiko Yamaguchi, Yoshiaki Sakurai, Nobuo Tamba, K. Watanabe, Masanori Odaka, Kazuo Kanetani
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:167-174
A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and writ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::724e7de536b7257d80caffc86a27cb9f
https://doi.org/10.1109/4.127339
https://doi.org/10.1109/4.127339
Autor:
Youji Idei, M. Odaka, Noriyuki Homma, Hiroaki Nambu, Kunihiko Yamaguchi, Toshiro Hiramoto, Kenichi Ohhata, Takahide Ikeda, Nobuo Tamba, Kazuo Kanetani, Yoshiaki Sakurai, K. Watanabe
Publikováno v:
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.
An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise;
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::765a680bd5e47b7f117a00ac7d7c7606
https://doi.org/10.1109/bipol.1992.274057
https://doi.org/10.1109/bipol.1992.274057
Autor:
Kenichi Ohhata, Youji Idei, Nobuo Tamba, Kazuo Kanetani, Noriyuki Homma, M. Odaka, Toshiro Hiramoto, Takahide Ikeda, Hiroaki Nambu, Kunihiko Yamaguchi, Yoshiaki Sakurai, K. Watanabe
Publikováno v:
Proceedings of the 1991 Bipolar Circuits and Technology Meeting.
A redundancy technique suitable for ultra-high-speed SRAMs is developed using focused-ion-beam and laser-chemical-vapor-deposition. This technique is applied to a 64 Kb SRAM with a 1.5 ns access time without deterioration of the ultra-high-speed char
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b634e7e6f8b53fcd8d7974aaadc3ec9a
https://doi.org/10.1109/bipol.1991.160972
https://doi.org/10.1109/bipol.1991.160972
Autor:
N. Yoshida, K. Miyamoto, T. Matsumoto, A. Wakahara, T. Ito, M. Sakamoto, H. Tanaka, T. Hiyama, T. Shimizu, Keiichi Higeta, Nobuo Tamba, R. Yamagata, K. Mori, K. Kurita, Mitsugu Kusunoki, H. Takahashi, N. Kato, Takeo Yamashita
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum sta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08363dd3c4769407deffae29f58b4773
https://doi.org/10.1109/isscc.2000.839839
https://doi.org/10.1109/isscc.2000.839839