Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Nobuo Hayasaka"'
Autor:
K. Muraoka, Hidetoshi Koike, E. Fukuda, S. Hohkibara, Nobuo Hayasaka, Hideshi Miyajima, K. Tomioka, M. Kimura, Fumiyoshi Matsuoka
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 11:54-62
We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot
Autor:
Keiji Horioka, Y. Akama, Haruo Okano, Nobuo Hayasaka, A. Sakai, S. Nadahara, J. Shiozawa, N. Shooda, Hirotaka Nishino
Publikováno v:
Journal of Applied Physics. 74:1349-1353
Changes in surface morphology have been studied for Si surfaces treated with CF4/O2 down‐flow etching. It has been found that rough Si surfaces can be smoothed and Si trench corners can be rounded off using this CF4/O2 down‐flow etching. A SiFxOy
Publikováno v:
Journal of Applied Physics. 74:1345-1348
Damage‐free selective etching of Si native oxides against Si has been achieved by NH3/NF3 and SF6/H2O down‐flow etching. In the NH3/NF3 etching, the wafer was covered with a film, and after its removal by heating above 100 °C, only SiO2 was foun
Autor:
Gaku Minamihaba, Yukiteru Matsui, Yoshikuni Tateyama, Atsushi Shigeta, Hiroyuki Yano, Nobuo Hayasaka, Takeshi Nishioka, K. Takahata
Publikováno v:
Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
In order to reduce the focus error for the stacked mask process (SMAP) used in Cu/low-k dual damascene (DD) interconnect, a planarization technology of the under layer film by CMP was developed. Photo-resist was used for the under layer film. CMP slu
Autor:
Sachiyo Ito, Takashi Yoda, H. Kamijo, M. Inohara, T. Hachiya, K. Akiyama, K. Tabuchi, Hideki Shibata, K. Watanabe, Hideshi Miyajima, K. Higashi, Shingo Kadomura, N. Matsunaga, Hisashi Yano, Akihiro Kajita, Nobuo Hayasaka, Toshiaki Hasegawa, Katsuyuki Fujita, R. Kanamura, T. Shimayama, Y. Enomoto, Rempei Nakata, K. Honda, Naofumi Nakamura
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
In order to realize highly reliable low-k/Cu interconnects, optimum BEOL structures were developed for 130, 90 and 65 node logic devices respectively. For 65 nm node BEOL structure, the conventional monolithic dual damascene (DD) structure was replac
Publikováno v:
Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
High performance low-k hybrid-DD structure (poly-arylene-ether (PAE)/ poly-methylsiloxane (MSX)) is realized by simultaneous electron beam (ebeam) curing technique, and applied to a 65 nm node Cu/low-k multilevel damascene process. By eBeam curing fo
Autor:
Masayoshi Kobayashi, Nobuo Hayasaka, Naoto Yoshitaka, Yoichi Ogawa, Tatsuhiko Higashiki, Shinichi Ito, Kenji Kawano, Kazuhiko Ishigo, Hideaki Kashiwagi, Hiroshi Ikegami
Publikováno v:
SPIE Proceedings.
We have successfully achieved accurate alignment to remove stacked TiN/Ti/Al/TiN/Ti films on damascene W marks by using laser ablation technology. Because, the Al films deposited on the damascene W marks lead to poor quality of alignment accuracy due
Autor:
Tetsuya Hamamoto, Shinichi Ito, Naoto Yoshitaka, Tomoyuki Takeishi, Kenji Kawano, Shoichi Terada, Hiroshi Ikegami, Masayoshi Kobayashi, Nobuo Hayasaka, Yoichi Ogawa
Publikováno v:
Advances in Resist Technology and Processing XX.
In the tri-level resist process, it is sometimes difficult to detect the alignment mark because of the anti-reflection performance of the organic thick anti-reflective (ARL). Laser ablation in running water was one of the most effective techniques fo
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
We present a high aspect ratio Al fill process using solid phase replacement (SPR). In contrast to earlier work in which polysilicon (poly-Si) was used, B-doped amorphous Si (a-Si:B) is used in this work to ensure application in multilevel Al interco
Publikováno v:
2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).
The achievement of rapid advances in integration density and performance of LSI devices is predicated on increasing the total number of Input/Output (I/O) and Power/Ground (P/G) terminals, which, in turn, leads to shrinking design rule of wiring and