Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Nobuki Kajihara"'
Autor:
Masaya Iwata, Shuji Yoshizawa, Nobuki Kajihara, Xin Yao, Masahiro Murakawa, Tetsuya Higuchi, Isamu Kajitani
Publikováno v:
IEEE Transactions on Computers. 48:628-639
This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the t
Autor:
Tetsuya Higuchi, Nobuki Kajihara
Publikováno v:
Communications of the ACM. 42:60-66
Autor:
Tetsuya Higuchi, Kenji Toda, Nobuyuki Otsu, Eiichi Takahashi, Masaya Iwata, H. Sakanashi, Isamu Kajitani, Didier Keymeulen, N. Salami, Nobuki Kajihara, Masahiro Murakawa
Publikováno v:
IEEE Transactions on Evolutionary Computation. 3:220-235
In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its
Autor:
Nobuki Kajihara, Masahiro Murakawa, Masaya Iwata, Didier Keymeulen, Daisuke Nishikawa, Hiroshi Yokoi, H. Sakanashi, Isamu Kajitani, Tetsuya Higuchi
Publikováno v:
Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems.
This paper describes an Evolvable Hardware (EHW) chip, and the application of this chip as a controller for a myoelectric prosthetic hand. The chip consists of Genetic Algorithm (GA) hardware, reconfigurable hardware logic, a chromosome memory, a tra
Publikováno v:
Evolvable Systems: From Biology to Hardware ISBN: 9783540426714
ICES
ICES
Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. However, there are problems
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d34f826e6f3830fd96e05aba6c47359
https://doi.org/10.1007/3-540-45443-8_4
https://doi.org/10.1007/3-540-45443-8_4
Publikováno v:
Field-Programmable Logic and Applications ISBN: 9783540424994
FPL
FPL
We have developed an ALU based reconfigurable device called RHW (Reconfigurable HardWare) that is designed to work with the CPU to accelerate the computation-intensive part of the application by reconfiguring its data paths and ALUs optimized for the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef2020297508b587d38473cf7cd5a1e8
https://doi.org/10.1007/3-540-44687-7_66
https://doi.org/10.1007/3-540-44687-7_66
Autor:
Masaya Iwata, Masahiro Murakawa, Nobuki Kajihara, Hidenori Sakanashi, Tetsuya Higuchi, Isamu Kajitani
Publikováno v:
Artificial Neural Nets and Genetic Algorithms ISBN: 9783211833643
ICANNGA
ICANNGA
This paper introduces two Evolvable Hardware LSIs for neural network applications. They are developed as part of MITI’s Real World Computing Project. One is self-reconfigurable neural network chip for ontogenic neural network processing, having the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::840c03ae1f42accf2a1f8fc31f03f19c
https://doi.org/10.1007/978-3-7091-6384-9_23
https://doi.org/10.1007/978-3-7091-6384-9_23
Autor:
Didier Keymeulen, Tsutomu Hoshino, Nobuki Kajihara, Isamu Kajitani, Takeshi Inuo, Daisuke Nishikawa, Shougo Nakaya, Tsukasa Yamauchi, Tetsuya Higuchi, Masaya Iwata, Hiroshi Yokoi
Publikováno v:
Evolvable Systems: From Biology to Hardware ISBN: 9783540649540
ICES
ResearcherID
ICES
ResearcherID
The advantage of Evolvable Hardware (EHW) over traditional hardware is its capacity for dynamic and autonomous adaptation, which is achieved through by Genetic Algorithms (GAs). In most EHW implementations, these GAs are executed by software on a per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::be478fc127a968de8172ff0a529a9c02
https://doi.org/10.1007/bfb0057602
https://doi.org/10.1007/bfb0057602
Publikováno v:
Systems and Computers in Japan. 20:31-38
MAN-YO is a special-purpose parallel computing machine being developed for logic circuit design and simulation. It uses dedicated hardware to increase the speed of gate-level simulation, and a combination of dedicated microprograms and processors for
Publikováno v:
Neural Networks. 1:544