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pro vyhledávání: '"Nithin Kumar Yernad Balachandra"'
Autor:
Sithara Raveendran, Nithin Kumar Yernad Balachandra, Pranose J. Edavoor, Vasantha Moodabettu Harishchandra
Publikováno v:
IET Image Processing. 14:4110-4121
This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image wi
Publikováno v:
Telecommunication Systems. 68:621-630
Due to performance and reliability, network on chip (NoC) is considered to be the future generation interconnect technique for multiple cores in a chip. This paper proposes a system level core mapping technique which improves the performance of the w
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra
Publikováno v:
Sustainable Computing: Informatics and Systems. 16:1-10
Network on Chip (NoC) has been proposed as an efficient solution to communication problems in on-chip processors. The probability of failure increases in these systems because the complexity involved in continuous device scaling and the number of com
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra
Publikováno v:
Microelectronics Journal. 70:16-26
This paper proposes a fault-tolerance network on chip (FTNoC) algorithm that incorporates a core graph unit, which is responsible for mapping and scheduling the core graph on the NoC architecture. Fault tolerance unit collects all the fault informati
Autor:
Nithin Kumar Yernad Balachandra, Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra
Publikováno v:
Wireless Personal Communications. 100:213-225
Extensive research has been conducted on task scheduling and mapping on a multi-processor system on chip. The mapping strategy on a network on chip (NoC) has a huge effect on the communication energy and performance. This paper proposes an efficient
Autor:
Ahish, Shylendra, Sharma, Dheeraj, Nithin Kumar, Yernad Balachandra, Vasantha, Moodabettu Harishchandra
Publikováno v:
IEEE Transactions on Electron Devices; Jan2016, Vol. 63 Issue 1, p288-295, 8p