Zobrazeno 1 - 10
of 254
pro vyhledávání: '"Nitayama, A."'
Autor:
Kumura, Y., Ozaki, T., Kanaya, H., Hidaka, O., Shimojo, Y., Shuto, S., Yamada, Y., Tomioka, K., Yamakawa, K., Yamazaki, S., Takashima, D., Miyakawa, T., Shiratake, S., Ohtsuki, S., Kunishima, I., Nitayama, A.
Publikováno v:
In Solid State Electronics 2006 50(4):606-612
Autor:
Shuso Fujii, Daisaburo Takashima, Ryu Ogiwara, Daisuke Hashimoto, Akihiro Nitayama, Shinichiro Shiratake, Ryo Fukuda, Susumu Shuto, Yohji Watanabe, Hidehiro Shiga, Tohru Ozaki, Katsuhiko Hoya, Iwao Kunishima, Tadashi Miyakawa, Sumiko Doumae, Takeshi Hamamoto, Hiroyuki Kanaya, Ryosuke Takizawa, Koji Yamakawa
Publikováno v:
ISSCC
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5daa454ca9ff7463fb3e94791bd14491
https://doi.org/10.1109/jssc.2011.2159053
https://doi.org/10.1109/jssc.2011.2159053
Autor:
Shinichiro Shiratake, Yoshinori Kumura, S. Ohtsuki, Hitoshi Shiga, Sumiko Doumae, Iwao Kunishima, T. Ozaki, Daisaburo Takashima, Tadashi Miyakawa, Ryu Ogiwara, Akihiro Nitayama, Koji Yamakawa, Katsuhiko Hoya, Syuso Fujii, Susumu Shuto
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1745-1752
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a05654e47ec1032b385902092e35fa7e
https://doi.org/10.1109/tvlsi.2009.2034380
https://doi.org/10.1109/tvlsi.2009.2034380
Autor:
Akihiro Nitayama, Tomoki Higashi, Hiroomi Nakajima, Takashi Ohsawa, Yoshihiro Minami, Takeshi Hamamoto, Yoshiaki Fukuzumi, Tomoaki Shino
Publikováno v:
IEEE Transactions on Electron Devices. 57:1781-1788
The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data “0” to data “1” has been observed in the writing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f3db14e000ade02991fdf045ae17998
https://doi.org/10.1109/ted.2010.2050550
https://doi.org/10.1109/ted.2010.2050550
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414
Autor:
H. Furuhashi, Yohji Watanabe, Tohru Furuyama, Takeshi Hamamoto, Hiroomi Nakajima, Akihiro Nitayama, Tomoaki Shino, Fumiyoshi Matsuoka, Yoshihiro Minami, Ryo Fukuda, Tomoki Higashi, Takashi Ohsawa, Katsuyuki Fujita
Publikováno v:
IEEE Transactions on Electron Devices. 56:2302-2311
Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a90a17948e6df6d7ac70923e8f5c011
https://doi.org/10.1109/ted.2009.2028396
https://doi.org/10.1109/ted.2009.2028396
Autor:
Yoshihiro Minami, Naoki Kusunoki, Akihiro Nitayama, Takeshi Hamamoto, Tomoaki Shino, Katsuyuki Fujita, A. Sakamoto, Hiroomi Nakajima, Takashi Ohsawa, T. Yamada, Mutsuo Morikado, K. Inoh, Tomoki Higashi, Kosuke Hatsuda
Publikováno v:
IEEE Transactions on Electron Devices. 54:563-571
A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ec0ce53161450f59be76c3576054aef
https://doi.org/10.1109/ted.2006.890597
https://doi.org/10.1109/ted.2006.890597
Autor:
Kazuhiro Tomioka, Yoshiro Shimojo, Tadashi Miyakawa, Koji Yamakawa, Daisaburo Takashima, Yoshinori Kumura, Yuki Yamada, S. Ohtsuki, O. Hidaka, Hiroyuki Kanaya, Iwao Kunishima, Shinichiro Shiratake, Akihiro Nitayama, Susumu Shuto, T. Ozaki, S. Yamazaki
Publikováno v:
Solid-State Electronics. 50:606-612
A damage-robust SrRuO 3 /IrO 2 top electrode FeRAM with Cu BEOL process is demonstrated for the first time as a promising device for 130 nm CMOS embedded non-volatile memory. The ferroelectric capacitor with SrRuO 3 /IrO 2 top electrode has no degrad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27c377a4dec5649f15355602b547c2dd
https://doi.org/10.1016/j.sse.2006.03.015
https://doi.org/10.1016/j.sse.2006.03.015
Autor:
Takashi Ohsawa, K. Inoh, Mutsuo Morikado, Tomoaki Shino, Akihiro Nitayama, Takeshi Hamamoto, Naoki Kusunoki, Katsuyuki Fujita, Hiroomi Nakajima, Tomoki Higashi, Yoshihiro Minami
Publikováno v:
IEEE Transactions on Electron Devices. 52:2220-2226
A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale mem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1605770255741bf245ed7dd11b9b502
https://doi.org/10.1109/ted.2005.856808
https://doi.org/10.1109/ted.2005.856808
Publikováno v:
AIJ Journal of Technology and Design. 10:71-76
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78afb891644cc735ff70baa478c8e240
https://doi.org/10.3130/aijt.10.71
https://doi.org/10.3130/aijt.10.71