Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Nishath Verghese"'
Autor:
Nishath Verghese, Makoto Nagata
Publikováno v:
EDA for IC Implementation, Circuit Design, and Process Technology ISBN: 9781315221694
Industrial Information Technology ISBN: 9780849379246
Industrial Information Technology ISBN: 9780849379246
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8e0c6a988f250e40e6e082c4370651af
https://doi.org/10.1201/b19714-30
https://doi.org/10.1201/b19714-30
Publikováno v:
Proceedings of the IEEE. 94:2109-2138
Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df2f8ed06da6e4c0f16c594b982d5eec
https://doi.org/10.1109/jproc.2006.886029
https://doi.org/10.1109/jproc.2006.886029
Publikováno v:
Wireless Networks. 4:41-53
This paper discusses design trade-offs for mixed-signal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corru
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c235202298ac96db400a9e5705c62ca0
https://doi.org/10.1023/a:1019123132222
https://doi.org/10.1023/a:1019123132222
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:354-365
This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2dcafa99071a216f829f0a145ac7951b
https://doi.org/10.1109/4.494197
https://doi.org/10.1109/4.494197
Publikováno v:
SPIE Proceedings.
With process technologies advancing to 65nm, 45nm, and below, device timing uncertainty due to lithography and other process variations has easily exceeded 50% and is still growing. In this paper, we present the development of a variability methodolo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::afa267d8a3db65c69ab2b2acd3531800
https://doi.org/10.1117/12.848018
https://doi.org/10.1117/12.848018
Publikováno v:
SPIE Proceedings.
To address the variability challenges inherent to 45 and 32nm as early as possible, a model-based variability analysis has been implemented to predict lithography induced electrical variability in standard cell libraries, and this analysis was used o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a65ed597285b04ef9421a5361be2c757
https://doi.org/10.1117/12.813969
https://doi.org/10.1117/12.813969
Autor:
Yajun Ran, Mark E. Mason, Anand Rajaram, Robert Ritchie, Philippe Hurat, Bala Kasthuri, Nishath Verghese, Clive Bittlestone, Haizhou Chen, Arjun Rajagopal, Raguram Damodaran, Jac Condella, Mark Terry, Srinivas Swaminathan, Frank Cano
Publikováno v:
SPIE Proceedings.
The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0cac00d83a2c930841dde78418608ac
https://doi.org/10.1117/12.778836
https://doi.org/10.1117/12.778836
Autor:
Thierry Devoivre, Yorick Trouiller, Raphael Bingert, Michel Luc Cote, Richard Rouse, Philippe Hurat, Alain Aurand, Jean-Claude Marin, Nishath Verghese, Eric Balossier, Florent Vautrin
Publikováno v:
SPIE Proceedings.
Leveraging silicon validation, a model-based variability analysis has been implemented to detect sensitivity to systematic variations in standard cell libraries using a model-based solution, to reduce performance spread at the cell level and chip lev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24d633165acfb02ee4b77ff76e733e92
https://doi.org/10.1117/12.772897
https://doi.org/10.1117/12.772897
Autor:
Koya Sato, Takeshi Hamamoto, Toshiaki Yanagihara, Jac Condella, Nishath Verghese, Philippe Hurat, Toshiyuki Matsunaga, Atsushi Okamura, Naohiro Kobayashi, Tatsuya Maekawa
Publikováno v:
SPIE Proceedings.
With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e6e9d5b30d10c0a53e2db21f5045828
https://doi.org/10.1117/12.773013
https://doi.org/10.1117/12.773013
Publikováno v:
CICC
At 65 nm, device and interconnect features are well below the wavelength of light used to pattern them, and shape variations significantly impact circuit characteristics. A simulation methodology to predict changes in circuit characteristics due to s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ff7c713b6941fae08b6b527b8db6eaa
https://doi.org/10.1109/cicc.2007.4405800
https://doi.org/10.1109/cicc.2007.4405800