Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Niraj Subba"'
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 6:292-299
This paper presents a new integrated silicon-on-insulator (SOI) substrate-diode (SUBD) structure for an electrostatic-discharge (ESD) protection of the SOI I/O circuits. The diode is built under the buried oxide, within the substrate region of the SO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ea0d23f2bd1a1825cf506b7b7ad5a462
https://doi.org/10.1109/tdmr.2006.876587
https://doi.org/10.1109/tdmr.2006.876587
Autor:
Amit P. Marathe, Akram A. Salman, E. Zhao, Stephen G. Beebe, J. Zhang, Kurt Taylor, J. Chan, Niraj Subba
Publikováno v:
Solid-State Electronics. 48:1703-1708
In this paper we have discussed various reliability issues in developing cutting edge SOI technologies with ultra-thin gate dielectrics such as DC-HCI (hot carrier injection), TDDB, NBTI, and ESD. Floating body and body tied structures on partially d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ce1b5bd744d4f425debbd94866dfc5f4
https://doi.org/10.1016/j.sse.2004.05.003
https://doi.org/10.1016/j.sse.2004.05.003
Publikováno v:
Solid-State Electronics. 48:1417-1422
Transport in Si NMOSFETs with gate lengths from 48 to 23 nm is investigated by full-band Monte Carlo device simulation for three sets of devices: (I) unstrained Si control devices, (II) process matched strained Si devices, and (III) threshold voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c395e8c00b42a5fe2460d770e74089c1
https://doi.org/10.1016/j.sse.2004.02.016
https://doi.org/10.1016/j.sse.2004.02.016
Autor:
Ciby Thuruthiyil, Vineet Wason, A.B. Icel, Niraj Subba, Jung-Suk Goo, Y. Apanovich, Qiang Chen, Awanish Pandey, Tran Ly
Publikováno v:
2008 IEEE International SOI Conference.
Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology. First, the gate CV parameter extraction is challenging due to small values and many extrinsi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6e11133c8123860704b1e4d7f825b0b
https://doi.org/10.1109/soi.2008.4656340
https://doi.org/10.1109/soi.2008.4656340
Autor:
S. Balasubramanian, Niraj Subba, Priyanka Chiney, Ciby Thuruthiyil, Vineet Wason, A.B. Icel, S. Krishnan, Qiang Chen, M. Gupta, Jung-Suk Goo
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
Critical currents (ICRIT) extracted from the N-curves of a 6-T SRAM bit cell have been shown in recent research to be important and effective figures of merit for the cell?s stability and write-ability. SPICE models of cell transistors, therefore, no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62a850cd41962f76cb3066f23414e5af
https://doi.org/10.1109/icsict.2008.4734560
https://doi.org/10.1109/icsict.2008.4734560
Autor:
M. Gupta, Jung-Suk Goo, Priyanka Chiney, Sushant Suryagandh, Qiang Chen, Zhi-Yuan Wu, Tran Ly, Niraj Subba, Martin Radwin, A.B. Icel, Ciby Thuruthiyil, Vineet Wason
Publikováno v:
2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
Speculative SPICE models (also referred to as evaluation-level or guess models), which are extracted based on projected device electrical characteristics (called `targets?) rather than actual measurement data, are required to support concurrent IC de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f64c32c44dac1c02be927326ebe78e2
https://doi.org/10.1109/icsict.2008.4734534
https://doi.org/10.1109/icsict.2008.4734534
Autor:
Jung-Suk Goo, L. Zamudio, Ciby Thuruthiyil, B.Q. Chen, Niraj Subba, A.B. Icel, M. Gupta, J. Yonemura, Mario M. Pelella, Judy Xilin An, Zhi-Yuan Wu, S. Krishnan, Sushant Suryagandh
Publikováno v:
ESSCIRC
Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d40894c4b7ac457be001c89653471343
https://doi.org/10.1109/esscirc.2007.4430260
https://doi.org/10.1109/esscirc.2007.4430260
Autor:
A.B. Icel, Niraj Subba, Jung-Suk Goo, Martin Radwin, Qiang Chen, Vineet Wason, Sushant Suryagandh, Ciby Thuruthiyil, R.Y.K. Su, Judy Xilin An, Zhi-Yuan Wu, Tran Ly
Publikováno v:
2007 IEEE International Conference on Microelectronic Test Structures.
A new methodology is proposed to extract self-heating free I-V curves, including the substrate current, of SOI MOSFETs based on triple-temperature, regular DC measurement. It is verified to be accurate with Hspice simulations and suitable for SPICE m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd60116271e3ec9951c08a659405ff99
https://doi.org/10.1109/icmts.2007.374498
https://doi.org/10.1109/icmts.2007.374498
Publikováno v:
2004 Electrical Overstress/Electrostatic Discharge Symposium.
In this paper we will present a new integrated SOI substrate diode structure for ESD protection of SOI I/O circuits that is built under the buried oxide of the SOI wafer using a standard CMOS process. We will show that the protection level can reach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::300ef7f96df8f32a15f293926a685907
https://doi.org/10.1109/eosesd.2004.5272603
https://doi.org/10.1109/eosesd.2004.5272603
Conference
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