Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Nipanka Bora"'
Autor:
Hriday Das, Nipanka Bora
Publikováno v:
2023 4th International Conference on Computing and Communication Systems (I3CS).
Autor:
Nipanka Bora
Publikováno v:
Silicon. 14:4945-4954
This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). Th
Publikováno v:
Journal of Nano Research. 65:39-50
This paper presents an analytical model of various electrical parameters for an ultra thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT). The model works for all the regions of operation of the nanowire transistor
Publikováno v:
Journal of Nano Research. 64:123-134
This paper presents an analytical model for ultra scaled symmetric double gate (SDG) nanowire junctionless field effect transistor (JLFET), which includes charge quantization in all the regions of operation. This model is based on a first-order corre
Autor:
Nipanka Bora, Rupaban Subadar
Publikováno v:
Journal of Nanoelectronics and Optoelectronics. 14:1283-1289
Publikováno v:
Journal of Advanced Physics. 6:408-412
An Analytical Surface Potential Model for Highly Doped Ultrashort Asymmetric Junctionless Transistor
Autor:
Rupaban Subadar, Nipanka Bora
Publikováno v:
Advances in Communication, Devices and Networking ISBN: 9789811334498
Here, we present an analytical solution for surface potential of a heavily doped ultralow channel Double-Gate Asymmetric Junctionless Transistor (DG AJLT). The gate-oxide-thickness and flatband voltage asymmetry were taken into considerations; furthe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39b7e4226526171ea550d5bd8941ac25
https://doi.org/10.1007/978-981-13-3450-4_6
https://doi.org/10.1007/978-981-13-3450-4_6
Publikováno v:
2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS).
In this work, performance analysis of sub nanometer asymmetric junctionless transistor has been studied. Lateral offset is present between the gates in the double gate structure. A comprehensive device characteristic including potential variations, d
Publikováno v:
2016 IEEE 1st International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES).
In this paper, the effect High Temperature on the performance of a symmetric double gate junctionless transistor based inverter is analyzed. 3D simulations are performed using COGENDA 3D TCAD tool to investigate its switching characteristics, voltage
Autor:
Ratul Kr. Baruah, Nipanka Bora
Publikováno v:
Journal of Computational and Theoretical Nanoscience. 8:2025-2028