Zobrazeno 1 - 10
of 50
pro vyhledávání: '"Nikolaos Vassiliadis"'
Publikováno v:
International Journal of Computing. :102-109
Multimedia applications are characterized by a high number of data transfers and storage operations. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. In this paper, the effect of d
Autor:
Athanasios M. Demiris, Calliope Louisa Sotiropoulou, Liberis Voudouris, Christos Gentsos, Spyridon Nikolaidis, Nikolaos Vassiliadis
Publikováno v:
IEEE Transactions on Biomedical Circuits and Systems. 8:268-277
A machine vision implementation on a field-programmable gate array (FPGA) device for real-time microfluidic monitoring on Lab-On-Chips is presented in this paper. The machine vision system is designed to follow continuous or plug flows, for which the
Autor:
S. Blionas, Nikolaos Vassiliadis, Konstantinos Efstathiou, Ioannis Ramfos, Ciara K. O'Sullivan, Alex Fragoso, Alexios Birbas
Publikováno v:
Biosensors and Bioelectronics. 47:482-489
The architecture and design of a compact, multichannel, hybrid-multiplexed potentiostat for performing electrochemical measurements on continuously-biased electrode arrays is presented. The proposed architecture utilises a combination of sequential a
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 2:1-30
Coupling reconfigurable hardware accelerators with processors is an effective way to meet the performance and flexibility required to cope with modern embedded applications. The ARISE framework provides a systematic approach to extend a processor onc
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17:221-233
ARISE introduces a systematic approach for extending once an embedded processor to support thereafter the coupling of an arbitrary number of custom computing units (CCUs). A CCU can be a hardwired or a reconfigurable unit, which can be utilized follo
Publikováno v:
International Journal of Electronics. 94:481-500
In this paper, at a reconfigurable instruction set processor (RISP) is targeted, which tightly couples a coarse-grain reconfigurable functional unit (RFU) to a RISC processor. Furthermore, the architecture is supported by a flexible development frame
Publikováno v:
Scopus-Elsevier
In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain reconfigurable functional unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor elimi
Autor:
Spiridon Nikolaidis, Konstantinos Tatas, Ilias Pappas, H. Pournara, V. Kalenteridis, Nikolaos Vassiliadis, Dimitrios Soudris, K. Siozos, G. Koutroumpezis, Antonios Thanailakis, Stylianos Siskos
Publikováno v:
Microprocessors and Microsystems. 29:247-259
In this paper a complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: the fine-grain reconfigurable hardware platform (FPGA) on which the logic is implement
Autor:
H. Pournara, G. Koutroumpezis, Nikolaos Vassiliadis, Konstantinos Tatas, V. Kalenteridis, Konstantinos Siozios, Stilianos Siskos, Antonios Thanailakis, Ilias Pappas, Spiridon Nikolaidis, Dimitrios Soudris
Publikováno v:
IEICE Transactions on Information and Systems. :1369-1380
A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 μm CMOS technology. The detailed design an
Autor:
Konstantinos Tatas, Spiridon Nikolaidis, Nikolaos Vassiliadis, Kostas Siozios, Ilias Pappas, V. Kalenteridis, G. Koutroumpezis, H. Pournara, Dimitrios Soudris, Stylianos Siskos, Antonios Thanailakis
Publikováno v:
Journal of Physics: Conference Series. 10:352-356
A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set