Detecting denial-of-service hardware Trojans in DRAM-based memory systems

Autor: Heba Salem, Nigel Topham

Publikováno v: Salem, H & Topham, N 2022, Detecting denial-of-service hardware Trojans in DRAM-based memory systems . in Proceedings of the 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021) . Institute of Electrical and Electronics Engineers (IEEE), 28th IEEE International Conference on Electronics Circuits and Systems, Dubai, United Arab Emirates, 28/11/21 . https://doi.org/10.1109/ICECS53924.2021.9665634

DRAM latencies are inherently variable, potentially allowing a denial-of-service hardware Trojan (DoS HT) to degrade memory performance without becoming immediately obvious. This paper addresses the challenge of detecting a DoS HT that may have been

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4c179aed119f8fef39eb68cca2b5c287
https://www.pure.ed.ac.uk/ws/files/233492645/Detecting_denial_of_service_SALEM_DOA15092021_AFV.pdf

Fast and correct load-link/store-conditional instruction handling in DBT systems

Autor: Nigel Topham, Tom Spink, Brian Campbell, Martin Kristien, Ian Stark, Björn Franke, Susmit Sarkar, Igor Bohm

Publikováno v: Kristien, M, Spink, T, Campbell, B, Sarkar, S, Stark, I, Franke, B, Boehm, I & Topham, N 2020, ' Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems ', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 11, pp. 3544-3554 . https://doi.org/10.1109/TCAD.2020.3013048

Dynamic binary translation (DBT) requires the implementation of load-link/store-conditional (LL/SC) primitives for guest systems that rely on this form of synchronization. When targeting, e.g., $\times 86$ host systems, LL/SC guest instructions are t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a1b74869314eda3886532a7e36e67c37
https://hdl.handle.net/10023/20838

Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning

Autor: Nigel Topham, Vijay Nagarajan, Saumay Dublish

Publikováno v: Dublish, S, Nagarajan, V & Topham, N 2019, Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning . in 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) . Institute of Electrical and Electronics Engineers (IEEE), Washington, DC, USA, pp. 492-505, 25th IEEE International Symposium on High-Performance Computer Architecture, Washington D.C., District of Columbia, United States, 16/02/19 . https://doi.org/10.1109/HPCA.2019.00061
HPCA

GPUs employ a high degree of thread-level parallelism (TLP) to hide the long latency of memory operations. However, the consequent increase in demand on the memory system causes pathological effects such as cache thrashing and bandwidth bottlenecks.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eb587e5e2a7c803d5e81cf70b90eff26
https://hdl.handle.net/20.500.11820/6e5d9bb6-1361-4d07-8317-fbe3429626d6

Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs

Autor: Nigel Topham, Saumay Dublish, Vijay Nagarajan

Publikováno v: Dublish, S, Nagarajan, V & Topham, N 2017, Evaluating and Mitigating Bandwidth Bottlenecks Across the Memory Hierarchy in GPUs . in 2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) . Institute of Electrical and Electronics Engineers (IEEE), pp. 239-248, 2017 IEEE International Symposium on Performance Analysis of Systems and Software, Santa Rosa, United States, 24/04/17 . https://doi.org/10.1109/ISPASS.2017.7975295
ISPASS

GPUs are often limited by off-chip memory bandwidth. With the advent of general-purpose computing on GPUs, a cache hierarchy has been introduced to filter the bandwidth demand to the off-chip memory. However, the cache hierarchy presents its own band

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a7b38ea3b4882ea4347f597aa0271272
https://hdl.handle.net/20.500.11820/2d479e5f-245c-4b81-be9c-74c101a61062

Characterizing memory bottlenecks in GPGPU workloads

Autor: Vijay Nagarajan, Nigel Topham, Saumay Dublish

Publikováno v: Dublish, S, Nagarajan, V & Topham, N 2016, Characterizing memory bottlenecks in GPGPU workloads . in 2016 IEEE International Symposium on Workload Characterization (IISWC) . Institute of Electrical and Electronics Engineers (IEEE), Providence, RI, USA, pp. 1-2, 2016 IEEE International Symposium on Workload Characterization, Providence, United States, 25/09/16 . https://doi.org/10.1109/IISWC.2016.7581287
IISWC

GPUs are often limited by the off-chip memory bandwidth. With the advent of general-purpose computing on GPUs, cache hierarchy has been introduced to filter the bandwidth demand to the off-chip memory. However, the cache hierarchy presents its own ba

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6f46d50079f754d7e79f7450f125f08f
https://www.pure.ed.ac.uk/ws/files/28417670/103_Dublish_PID4414159_1.pdf