Model Checker Aided Design of a Controller for a Wafer Scanner

Autor: Hendriks, M., Nieuwelaar, N.J.M. van den, Vaandrager, F.W., Margaria, T., Steffen, B., Philippou, A., Reitenspiess, M.

Publikováno v: International Journal on Software Tools for Technology Transfer, 8, 633-647
International Journal on Software Tools for Technology Transfer, 8, 6, pp. 633-647
Margaria, T.; Steffen, B.; Philippou, A. (ed.), Preliminary Proceedings International Symposium on Leveraging Applications of Formal Methods (ISoLA 2004), rm October/November 2004, Paphos, Cyprus, 201-209. [S.l.] : Department of Computer Science, University of Cyprus
STARTPAGE=201;ENDPAGE=209;TITLE=Margaria, T.; Steffen, B.; Philippou, A. (ed.), Preliminary Proceedings International Symposium on Leveraging Applications of Formal Methods (ISoLA 2004), rm October/November 2004, Paphos, Cyprus
Margaria, T.; Steffen, B.; Philippou, A. (ed.), Preliminary Proceedings International Symposium on Leveraging Applications of Formal Methods (ISoLA 2004), rm October/November 2004, Paphos, Cyprus, pp. 201-209
International Journal on Software Tools for Technology Transfer, 8(6), 633-647. Springer

For a case-study of a wafer scanner from the semiconductor industry it is shown how model checking techniques can be used to compute (1) a simple yet optimal deadlock avoidance policy, and (2) an infinite schedule that optimizes throughput. in the ab

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f51e04800691ba8f36d811ecb516065e
https://doi.org/10.1007/s10009-006-0025-7