Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Nien-Hsiang Chang"'
Autor:
Hsun-Wei Chan, Yen-Cheng Kuan, Pei-Yun Tsai, Hsin-Ting Chang, Kang-Lun Chiu, Shyh-Jye Jou, Huang Zheng-Chun, Chih-Wei Jen, Henry Lopez, Hung-Chih Liu, Ngoc-Giang Doan, Nien-Hsiang Chang
Publikováno v:
A-SSCC
This paper presents a baseband (BB) transceiver for mm-Wave band with the proposed high-efficient built-in digital self-healing mechanism (SHM) that achieves a single stream of 10/15 Gbps throughput in 16/64 QAM single-carrier (SC) mode with a requir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::799f94b588e48b506f6b30d1f2dba091
https://doi.org/10.1109/a-sscc48613.2020.9336151
https://doi.org/10.1109/a-sscc48613.2020.9336151
Autor:
Hsun-Wei Chan, Shyh-Jye Jou, Kang-Lun Chiu, Chang-Ting Wu, Nien-Hsiang Chang, Chih-Wei Jen, Chun-Yi Liu, Meng-Yuan Huang, Tsai-Hua Lee, Yen-Cheng Kuan, Pei-Yun Tsai, Henry Lopez, Hsin-Ting Chang, Wei-Che Lee, Hung-Chih Liu
Publikováno v:
A-SSCC
In this paper, we introduce a 10 Gbps digital baseband transceiver with 1V supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f3f6589e677e3ee2a2cf5944fcbdfc7
https://doi.org/10.1109/a-sscc47793.2019.9056920
https://doi.org/10.1109/a-sscc47793.2019.9056920
Autor:
Nien-Hsiang Chang, Chun-Chieh Chu, Chih-Chyau Yang, Yi-Jun Liu, Chun-Ming Huang, Chien-Ming Wu, Wen-Ching Chen, Chih-Hsing Lin, Chun-Chieh Chiu
Publikováno v:
APCCAS
This paper proposes a modularized three-dimensional (3D) heterogeneous system integration platform architecture, namely, MorPACK (morphing package). The architecture of MorPACK platform achieves high performance and function flexibility with low sili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7dbccb2b0281c47cec5a4942317520dc
https://doi.org/10.1109/apccas.2012.6419055
https://doi.org/10.1109/apccas.2012.6419055
Autor:
Chun-Ming Huang, Shih-Lun Chen, Chih-Chyau Yang, Nien-Hsiang Chang, Chien-Ming Wu, Chi-Shi Chen, Wei-De Chien
Publikováno v:
SoCC
In this paper, a novel silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. For integrating heterogeneous SoC projects into a single chip, the current SoC methodology is insufficient due to the comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9178a03009c106f2f2f47e4e146abca3
https://doi.org/10.1109/socc.2011.6085090
https://doi.org/10.1109/socc.2011.6085090
Publikováno v:
ISCAS
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigurable computation array (RCA) can be landed with the features of high u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5cba4cc1f43fef2f0be859b6759259f
https://doi.org/10.1109/iscas.2006.1693000
https://doi.org/10.1109/iscas.2006.1693000
Autor:
Huang, Chun-Ming, Yang, Chih-Chyau, Wu, Chien-Ming, Chiu, Chun-Chieh, Liu, Yi-Jun, Chu, Chun-Chieh, Nien-Hsiang, Chang, Chen, Wen-Ching, Lin, Chih-Hsing, Luo, Hua-Hsin
Publikováno v:
2012 IEEE International SOC Conference; 1/ 1/2012, p78-82, 5p
Autor:
Chih-Chyau Yang, Nien-Hsiang Chang, Shih-Lun Chen, Wei-De Chien, Chi-Shi Chen, Chien-Ming Wu, Chun-Ming Huang
Publikováno v:
2011 IEEE International SOC Conference (SOCC); 2011, p308-311, 4p