Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Nicolas Pfeifer"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:5295-5303
The functional verification of multicore chips requires the generation of parallel test programs able to expose design errors and ensure high coverage in less time. Albeit the coherence hardware can scale gracefully as the number of cores grows, the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::faa0bc993b62d60f1c534425e25677b9
https://doi.org/10.1109/tcad.2020.2974343
https://doi.org/10.1109/tcad.2020.2974343
Publikováno v:
DATE
Multicore chips are expected to rely on coherent shared memory. Albeit the coherence hardware can scale gracefully, the protocol state space grows exponentially with core count. That is why design verification requires directed test generation (DTG)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99c5427b7467e4e034aecb7712a5f9e3
https://doi.org/10.23919/date48585.2020.9116198
https://doi.org/10.23919/date48585.2020.9116198
Publikováno v:
ICCAD
This paper proposes a framework for functional verification of shared memory that relies on reusable coverage-driven directed test generation. It reveals a new mechanism to improve the quality of non-deterministic tests. The generator exploits genera
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd0940057bc57d36251b28f15312e63a
https://doi.org/10.1145/3240765.3240852
https://doi.org/10.1145/3240765.3240852