Zobrazeno 1 - 10
of 53
pro vyhledávání: '"Nicolas Daval"'
Autor:
Enrica Cela, Sam Shahidi, Prasant Parangi, Ramesh Shrestha, Gavin Simpson, Julie Widiez, Nicolas Daval, Audrey Chapelle, Séverin Rouchier, Walter Schwarzenbach
Publikováno v:
Defect and Diffusion Forum. 425:57-61
SmartSiCTM technology enables the supply of cost-effective and high-quality substrates to support the manufacturing of Silicon Carbide (SiC) Power Devices and the transition to High Volume Manufacturing (HVM) [1]. As detailed in [2] SmartSiCTM is pre
Autor:
E. Cela, Christophe Maleville, Ludovic Ecarnot, C. Maddalon, Nicolas Daval, S. Loubriat, C. Bertrand-Giuliani, Walter Schwarzenbach, Bich-Yen Nguyen, G. Chabanne, M. Detard
Publikováno v:
IEEE Journal of the Electron Devices Society
Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm B
Autor:
Amy Child, Walter Schwarzenbach, Rick Carter, Robert Mulfinger, Bich-Yen Nguyen, Nicolas Daval, J. Kluth, Jamie Schaeffer, Manish Hemkar, S. Moffatt, G. Chabanne, Schubert S. Chu, Sherry Straub, Paul A. Clifton, Andreas Goebel, Ryan Sporer
We report for the first time the implementation of SiGe buried stressors in the context of research and development of an advanced foundry FDSOI process and the observation of improved transconductance and current drive performance of n-channel FDSOI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::52dbc92e222e6301545d2962f2b3794b
Publikováno v:
IEEE Transactions on Electron Devices. 60:3611-3617
This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manu
Autor:
Eugene Y.-J. Kong, Ran Cheng, Christelle Veytizou, Bich-Yen Nguyen, Pengfei Guo, Yee-Chia Yeo, Bin Liu, Qian Zhou, Nicolas Daval, Chunlei Zhan, Yue Yang, Daniel Delprat
Publikováno v:
IEEE Transactions on Electron Devices. 60:2135-2141
We report the first demonstration of a p-channel Ω-gate Germanium (Ge) multiple-gate field-effect transistor (MuGFET) on a Germanium-on-Insulator (GeOI) substrate with in situ Boron (B)-doped Ge (Ge:B) raised source/drain (RSD). Detailed process opt
Autor:
Chunlei Zhan, Yee-Chia Yeo, Bich-Yen Nguyen, Genquan Han, Jie Li, Nicolas Daval, Daniel Delprat, Christelle Veytizou, Yongdong Liu, Hock-Chun Chin, Jiangtao Hu, Xiao Gong, Bin Liu, Moh-Lung Ling
Publikováno v:
IEEE Transactions on Electron Devices. 60:1852-1860
We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping conc
Publikováno v:
Solid-State Electronics. 83:37-41
We report a novel way of introducing strain in Ultra-Thin Body and Buried-Oxide (UTBB) SOI structures by Ge + implant into the underlying Si substrate and the formation of localized SiGe regions underneath the buried oxide (BOX) by Crystallization. T
Autor:
O. Bonnin, C. Maleville, Nicolas Daval, By. Nguyen, X. Cauchy, Walter Schwarzenbach, V. Barec
Publikováno v:
ECS Transactions. 50:53-57
Devices using fully depleted undoped channels are among the most promising candidates for the next device generations due to their better immunity to short channel effects (SCE) (1) and to random dopant fluctuation. Channel engineering and control ar
Publikováno v:
ECS Journal of Solid State Science and Technology. 2:Q83-Q87
Fully Depleted (FD) devices provide the electrostatic boost that is required to manufacture CMOS technology with printed gate lengths 25 nm and below, with the additional benefit of improved variability due to the ability of these devices to operate
Autor:
Konstantin Bourdelle, B. Previtali, David Cooper, P. Scheiblin, C. Tabone, Cecile Aulnette, M. Valenza, F. Allain, Mikael Casse, Jean-Francois Damlencourt, J. Gyani, Bich-Yen Nguyen, L. Brevard, Christophe Figuet, Pierre Perreau, Olivier Weber, S. Baudot, Nicolas Daval, C. Le Royer, Francois Andrieu, C. Rauer
Publikováno v:
Solid-State Electronics. :9-15
We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI with a TiN/HfO 2 gate stack (EOT = 1.15 nm) and down to 40 nm gate lengths. We demonstrate