Zobrazeno 1 - 10
of 37
pro vyhledávání: '"Nicolas Breil"'
Autor:
Claire Marais-Sicre, Solen Queguiner, Vincent Bustillo, Luka Lesage, Hugues Barcet, Nathalie Pelle, Nicolas Breil, Benoit Coudert
Publikováno v:
Remote Sensing, Vol 16, Iss 8, p 1436 (2024)
Unmanned aerial vehicles (UAVs) provide images at decametric spatial resolutions. Their flexibility, efficiency, and low cost make it possible to apply UAV remote sensing to multisensor data acquisition. In this frame, the present study aims at emplo
Externí odkaz:
https://doaj.org/article/b1e507449076428b8d7b9eaaa8554628
Autor:
Nicolas Breil
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
In this invited paper, we demonstrate that the contact interface resistance is a major bottleneck for advanced FinFET performance scaling (38% of the external resistance at 45nm gate pitch). After analyzing the key components defining the contact int
Autor:
N. H. Yang, S. Salimian, C. I. Li, J. Kuo, T. Y. Wen, S. Tang, Kelly E Hollar, B.N. Guo, M. Hou, Shashank Sharma, J. Y. Wu, H. Nejad, S. Nagy, S. H. Tsai, Ben Ng, C. Wang, Hans-Joachim L. Gossmann, M. S. Hsieh, Raymond Hung, G. C. Hung, Fareen Adeni Khaja, D. Liao, S. C. Hsu, J. Wen, Michael Chudzik, Kyu-Ha Shim, C. W. Chang, S. Y. Liu, Nicolas Breil, S.-C. Chen, S. J. Yen, Naushad Variam
Publikováno v:
IEEE Electron Device Letters. 40:307-309
This letter reports a new method using boron plasma doping and nanosecond laser annealing for further improvement of contact engineering. Up to 8% device performance improvement is demonstrated by using this technique in a conventional FinFET archite
Autor:
Xi-Wei Lin, Nicolas Breil, Michael Chudzik, Chidi Chidambaram, S. C. Song, Munkang Choi, Victor Moroz, Benjamin Colombeau, Qiang Lu, Giri Nallapati, Jerry Bao, Peijie Feng, John Jianhong Zhu
Publikováno v:
IEEE Electron Device Letters. 38:1657-1660
This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) archi
Autor:
Jean S. Jordan Sweet, Christian Lavoie, Adra Carr, Elisabeth Levrau, Nicolas Breil, Emre Alptekin, Ahmet S. Ozcan, Praneet Adusumilli
Publikováno v:
ECS Transactions. 77:59-79
With the continued evolution of CMOS technologies, which includes recent changes in both device geometries and contact schemes, contact lengths of advanced devices are now reaching below 20 nm. At these dimensions, material microstructure (grain size
Autor:
Jennifer Tseng, Nikolaos Bekiaris, Amir Wachs, Abhinav Kumar, Dror Shemesh, Raymond Hung, Kuchik Vadim, K. Nafisi, Jonathan R. Bakke, Michael Chudzik, A. Litman, A. Karnieli, Nicolas Breil, Mehul Naik, Jin Hee Park, N. Khasgiwale, Jorge Pablo Fernandez
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Inline detection of embedded voids within Middle-Of-Line (MOL) cobalt metal lines is a major industry gap at 7nm technology node and below, for both developing the new metallization solutions, as well as for monitoring during ramp and production. We
Autor:
Jean Jordan-Sweet, Karen A. Nummy, Bing Sun, Christian Lavoie, Frieder H. Baumann, N. Klymko, Jian Yu, Nicolas Breil, Michael P. Chudzik, Shreesh Narasimha, Frank Zhu, Ahmet S. Ozcan
Publikováno v:
Microelectronic Engineering. 137:79-87
Display Omitted The evolution of CMOS technologies and of the silicidations techniques are described.A peculiar nickel monosilicide defect termed NiSi-Fang is detected and characterized.The NiSiGe formation is investigated on Si, SiGe materials and (
Autor:
Jean Jordan-Sweet, Michael Chudzik, J. Ye, Christian Lavoie, Robin Chao, W. Wang, Charan V. V. S. Surisetty, Adra Carr, K. D. Chiu, Kuratomi Takashi, Shashank Sharma, E. Levrau, I-Cheng Chen, Raymond Hung, Avgerinos V. Gelatos, M. Stolfi, Nicolas Breil, H. Van Meer, Nicolas Loubet, Ahmet S. Ozcan
Publikováno v:
2017 Symposium on VLSI Technology.
We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B cont
Autor:
G. C. Hung, D. Liao, D. Tsai, C. T. Tsai, J. Kuo, Nicolas Breil, J. Wen, T.R. Yew, C.Y. Yang, J. Ren, J. Hebb, Osbert Cheng, J. Y. Wu, S. C. Hsu, S.H. Lin, J.H. Park, J. Hsieh, F. Chiang, Chi-Nung Ni, N. H. Yang, Naushad Variam, S. Chen, Benjamin Colombeau, J.F. Lin, Shashank Sharma, H.F. Huang, Y.R. Yang, Michael Chudzik, G. Leung, Kyu-Ha Shim, B.N. Guo, M. Hou, Hao Chen
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the so
Autor:
Praneet Adusumilli, B. Zhang, Chanro Park, B. Liu, Jin Cai, Balasubramanian S. Pranatharthi Haran, J. J. An, D. Ferrer, E. Engbrecht, Ahmet S. Ozcan, Hiroaki Niimi, R. Divakaruni, Y. Yan, R. Bolam, Huiming Bu, F. Chafik, Bruce B. Doris, S. Stiffler, Dechao Guo, B. Morgenfeld, Henry K. Utomo, Nicolas Loubet, N. Zhan, D. Hilscher, Jeffrey C. Shearer, W. Henson, C. Tran, C-H. Lin, James Chingwei Li, M. Oh, Hemanth Jagannathan, Jody A. Fronheiser, D. Kang, Ruilong Xie, T. Nesheiwat, Zuoguang Liu, Ravikumar Ramachandran, S. Allen, Walter Kleemeier, Oleg Gluschenkov, J. Rice, R. Lallement, Christian Lavoie, Jiseok Kim, Nicolas Breil, Siyuranga O. Koswatta, Emre Alptekin, C. Goldberg, Noah Zamdmer, Shogo Mochizuki, Veeraraghavan S. Basker, Gen Tsutsui, Keith Kwong Hon Wong, S. Fan, N. Makela, S. Jain, James J. Demarest, Christopher D. Sheraw, C.-C. Yeh, Mark Raymond, Anil Kumar, Yoo-Mi Lee, Vamsi Paruchuri, V. Sardesai, Vimal Kamineni, Woo-Hyeong Lee, Y. Ke, M. Yu, Andre Labonte, Tenko Yamashita, C. Niu, S. Narasimha
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & d