Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Nicola Caselli"'
Publikováno v:
IET Computers & Digital Techniques
Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3b25bbe028000ae64f62732758cbe6a4
http://hdl.handle.net/11392/1733898
http://hdl.handle.net/11392/1733898
Publikováno v:
MCSoC
This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) for bisynchronous communication channels. Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test