Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Nicky Chau-Chun Lu"'
Autor:
Tsung-Ming Wu, Nicky Chau-Chun Lu, Chun Shiah, Gang-Jhih Fan, Tzong-Lin Wu, Meng-Lin Wu, Chao-Kai Chan
Publikováno v:
2020 IEEE 24th Workshop on Signal and Power Integrity (SPI).
In this paper, the design tips considering power integrity (PI) for the power distribution network (PDN) in an re-distribution layer (RDL) are presented. First, the methodology of chip-RDL co-simulation is introduced. It indicates that decreasing the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0da0fc5c99818e4f2610ff6d03072e82
https://doi.org/10.1109/spi48784.2020.9218219
https://doi.org/10.1109/spi48784.2020.9218219
Autor:
W.M. Huang, K.C. Ting, Cheng-Nan Chang, Rick Dai, Ho-Yin Chen, C.P. Chuang, Nicky Chau-Chun Lu, Richard Crisp, W.J. Huang, C.N. Pan, C.P. Lin, S.H. Jheng, T.F. Chang, Chun Shiah, Bor-Doou Rong
Publikováno v:
VLSI Circuits
A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed40854b5966f14cb4e7ccfe892bf938
https://doi.org/10.23919/vlsic.2019.8778049
https://doi.org/10.23919/vlsic.2019.8778049
Autor:
Tzong-Lin Wu, Chun Shiah, Gang-Jhih Fan, Meng-Lin Wu, Tsung-Ming Wu, Chao-Kai Chan, Nicky Chau-Chun Lu
Publikováno v:
2018 IEEE International Conference on Computational Electromagnetics (ICCEM).
In this paper, a simulation methodology considering signal integrity (SI) and power integrity (PI) from the chip, package, and board levels of a double-data-rate three (DDR3) memory module is presented. For SI issues, the chip-package-board simulatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::672e68f9a9c166367c4ba4fb932e8d50
https://doi.org/10.1109/compem.2018.8496538
https://doi.org/10.1109/compem.2018.8496538
Autor:
Po-Lin Shih, Yu-Hui Sung, Shih-Lien Lu, Cheng-Wen Wu, Nicky Chau-Chun Lu, Chia-Hsin Lee, Chun-Nan Lu, Mei-Chiang Lung, Chi-Kang Chen, Wei Wu, Chun Shiah, Bor-Doou Rong, Kuo-Hua Lee, Ming-Wei Li, Yung-Fa Chou, Patrick F. Stolt, H.C. Shih, Pei-Wen Luo, Chung-Hu Ke, Ding-Ming Kwai, Shigeki Tomishima
Publikováno v:
VLSIC
Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2737e611543092841174007bb2fef60
https://doi.org/10.1109/vlsic.2015.7231256
https://doi.org/10.1109/vlsic.2015.7231256
Autor:
Ken Takeuchi, Nicky Chau-Chun Lu
Publikováno v:
2010 IEEE International Solid-State Circuits Conference - (ISSCC).
This session combines DRAM and NAND Flash memory, which are the two work-horses of the memory industry. Some of the exciting advances that have allowed the adoption of these memory technologies in a variety of consumer electronics are revealed in thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6fccafba7a6a1a1cd3f36b24f8dafdd0
https://doi.org/10.1109/isscc.2010.5433881
https://doi.org/10.1109/isscc.2010.5433881
Autor:
Sreedhar Natarajan, Nicky Chau-Chun Lu
Publikováno v:
ISSCC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bab12507c46d8d9884577017350f9225
https://doi.org/10.1109/isscc.2008.4523104
https://doi.org/10.1109/isscc.2008.4523104
Autor:
T.J. Bucelot, Keith A. Jenkins, R.L. Franch, Walter H. Henkels, Nicky Chau-Chun Lu, Wei Hwang, T.V. Rajeevakumar, M.J. Immediato, David F. Heidel
Publikováno v:
International Symposium on VLSI Technology, Systems and Applications.
Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the res
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a4af1cf30a0b439f674f7f927acd081
https://doi.org/10.1109/vtsa.1989.68576
https://doi.org/10.1109/vtsa.1989.68576
Autor:
T.V. Rajeevakumar, B.J. Ginsberg, E.J. Sprogis, B.J. Machesney, Nicky Chau-Chun Lu, G.B. Bronner
Publikováno v:
Technical Digest., International Electron Devices Meeting.
A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e17e1938fa3e9122a55933f2a5a5f5fb
https://doi.org/10.1109/iedm.1988.32883
https://doi.org/10.1109/iedm.1988.32883
Publikováno v:
IEEE Electron Device Letters; 1981, Vol. 2 Issue 4, p95-98, 4p
Publikováno v:
IEEE Journal of Solid-State Circuits. 23:34-40
A significant improvement in sensing speed over the half-V/sub DD/ bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V/sub DD/. The 2/3-V/sub DD/ sensing scheme also results in higher-bit-line capacitance,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ff43b99df4d47ef2f1598f85172e866
https://doi.org/10.1109/4.253
https://doi.org/10.1109/4.253