Výsledky vyhledávání - "Nick Lindert"

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Autor: Manoj B. Lal, Umut Arslan, Shigeki Tomishima, Fatih Hamzaoglu, Nick Lindert, Yih Wang, Kevin Zhang, Nabhendra Bisnik, Swaroop Ghosh, Randy B. Osborne, Mesut Meterelliyoz, Joodong Park

Publikováno v: IEEE Journal of Solid-State Circuits. 50:150-157

An embedded DRAM (eDRAM) integrated into 22 nm CMOS logic technology using tri-gate high-k metal gate transistor and MIM capacitor is described. A 1 Gb eDRAM die is designed, which includes fully integrated programmable charge pumps to over- and unde

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::46d7140873638321cc259e315a044e0c
https://doi.org/10.1109/jssc.2014.2353793

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Moore's law lives on [CMOS transistors]

Autor: Yang-Kyu Choi, Jeffrey Bokor, Chenming Hu, Peiqi Xuan, Tsu-Jae King, J. Kedzierski, Nick Lindert, Leland Chang

Publikováno v: IEEE Circuits and Devices Magazine. 19:35-42

We discuss several device structures suitable for scaling CMOS devices well into the nano-CMOS era, perhaps down below 10 nm physical gate length. The ultra-thin body MOSFET device structure has many features in common with today's bulk MOSFET, which

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cea09822522d914ceb14510e04beaa2d
https://doi.org/10.1109/mcd.2003.1175106

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Integration of a 3-D capacitor into a logic interconnect stack for high performance embedded DRAM SoC technology

Autor: J. Neulinger, Nick Lindert, Yih Wang, H.-P. Chen, L. Rockford, J. Peach, Ruth A. Brain, Kevin Zhang, Nabhendra Bisnik

Publikováno v: IEEE International Interconnect Technology Conference.

A 22 nm generation technology is described incorporating transistor and interconnects with performance suitable for the needs of both high density DRAM and high-performance logic devices. We have integrated a 0.029 µm2 DRAM cell capable of meeting >

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f74398bb2c9817e25c9b182e5bcd7d33
https://doi.org/10.1109/iitc.2014.6831892

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Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Autor: Shigeki Tomishima, Yih Wang, Fatih Hamzaoglu, Nick Lindert, Umut Arslan, Joodong Park, Ruth A. Brain, Mesut Meterelliyoz, Kevin Zhang, Swaroop Ghosh, Nabhendra Bisnik

Publikováno v: 2013 IEEE International Electron Devices Meeting.

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::76204ca48be1b1676c7df8b2bfcaf969
https://doi.org/10.1109/iedm.2013.6724595

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A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

Publikováno v: 2010 Symposium on VLSI Technology.

A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achie

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1b6b5e40107c1a394af62bae286b1d46
https://doi.org/10.1109/vlsit.2010.5556201

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A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

Publikováno v: 2008 IEEE International Electron Devices Meeting.

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::650637eed7ee1291376a576974fdaa08
https://doi.org/10.1109/iedm.2008.4796772

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A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications

Autor: G. Curello, K. Komeyli, Nick Lindert, J. Rizk, G. Sacks, S. Gannavaram, P. Bai, J. Lin, C.-H. Jan, D. Yeh, Joodong Park, Ian R. Post, U. Jalan, C. Tsai, Muhammad Akbar, Hafez Walid M

Publikováno v: 2006 International Electron Devices Meeting.

Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve fT/fMAX values of 360 GH

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c651ea657b290d7d8a502d4261783987
https://doi.org/10.1109/iedm.2006.346816

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An advanced low power, high performance, strained channel 65nm technology

Publikováno v: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

An advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented. At 1V and off current of 100nA/mum, transistors have record currents of 1.21mA/mum and 0.71mA/mum for NMOS and PMOS respectivel

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a2561b0a164894fb218016f264ba3ed8
https://doi.org/10.1109/iedm.2005.1609318

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