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pro vyhledávání: '"Nevin Kirman"'
Autor:
Nevin Kirman, Jose F. Martinez
Publikováno v:
ASPLOS
We present an all-optical approach to constructing data networks on chip that combines the following key features: (1) Wavelength-based routing, where the route followed by a packet depends solely on the wavelength of its carrier signal, and not on i
Publikováno v:
ISCA
This paper presents core fusion, a reconfigurable chip multiprocessor(CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run tim
Autor:
Alyssa B. Apsel, Nevin Kirman, David H. Albonesi, Meyrem Kirman, Rajeev K. Dokania, Matthew A. Watkins, Jose F. Martinez
Publikováno v:
IEEE Micro. 27:56-66
This work investigates the integration of CMOS-compatible optical technology to on-chip coherent buses for future CMPs. The analysis results in a hierarchical optoelectrical bus that exploits the advantages of optical technology while abiding by proj
Publikováno v:
IPDPS
We present core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, or they can be used as distinct processing elements, as needed at run time by app
Publikováno v:
MICRO
The performance of computer systems varies over the course of their execution. A system may perform well dur- ing some parts of its execution and poorly during others. To understand why a system behaves in this way performance analysts need to study
Autor:
Nevin Kirman, Jose F. Martinez, Rajeev K. Dokania, Alyssa B. Apsel, David H. Albonesi, Matthew A. Watkins, Meyrem Kirman
Publikováno v:
MICRO
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate t
Publikováno v:
MICRO
Checkpointed early resource recycling (Cherry) is a recently-proposed microarchitectural technique that aims at improving critical resource utilization by performing aggressive resource recycling decoupled from instruction retirement, using a checkpo
Publikováno v:
HPCA
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions, they also prevent other instructions from moving through the in-order reord