Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Netanel Shavit"'
Publikováno v:
IEEE Access, Vol 11, Pp 116206-116218 (2023)
In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces improvements at both the architecture and logic gate levels, by capi
Externí odkaz:
https://doaj.org/article/4aed7f682b5b46a4a39f3bb179cfb16f
Autor:
Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Leonid Yavits, Itamar Levi, Alexander Fish
Publikováno v:
IEEE Solid-State Circuits Letters. 6:73-76
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:596-608
Publikováno v:
IEEE Solid-State Circuits Letters. 3:314-317
The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by
Publikováno v:
ISCAS
This demo demonstrates the unique capabilities of the multimode Dual Mode Logic (DML) design technique to define run-time adaptive datapaths to overcome process and environmental (i.e., temperature and voltage) variations. A proof-of concept benchmar
Publikováno v:
ISCAS
The Dual Mode Logic (DML) defines run-time adaptive digital architectures that switch to either improved performance or lower energy consumption as a function of actual computational workload. This flexibility is demonstrated for the first time by si
Publikováno v:
ISCAS
In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique charac
Publikováno v:
ISCAS
Scopus-Elsevier
Scopus-Elsevier
Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. O
Publikováno v:
2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE).
Previous work on Dual Mode Logic (DML) have demonstrated improvements in frequency and energy compared to CMOS. In this paper, for the first time, we examine scaling of the DML circuits and present an evaluation of DML in 28nm bulk technology. The im
Publikováno v:
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Dual Mode Logic (DML), which was recently introduced by our group, offers the possibility to operate digital gates either in the static mode to save energy, or in the dynamic mode to increase speed albeit with a higher delay or energy consumption, re