Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Nestor Tzartzanis"'
Autor:
Nestor Tzartzanis, Mariko Sugawara, Masaya Kibune, Yoshiyasu Doi, Yukito Tsunoda, Scott McLeod, Anders Kristensson, H. Tamura, Subodh M. Reddy, Satoshi Ide, William F. Walker, Tetsuji Yamabana, Kouichi Kanda, Nikola Nedovic, Satoshi Matsubara, Samir Parikh, Junji Ogawa, Takayuki Hamada, T. Yamamoto, Tadashi Ikeuchi, Takayuki Shibasaki, Naoki Kuwata, Yasumoto Tomita
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:2016-2029
A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cc5fda0900971ac3eb33240e0b3418d
https://doi.org/10.1109/jssc.2010.2057970
https://doi.org/10.1109/jssc.2010.2057970
Autor:
M. Wiklund, Y. Okaniwa, Y. Mizutani, William W. Walker, Nestor Tzartzanis, H. Tamura, F.M. Rotella, Tadahiro Kuroda, Junji Ogawa, Nikola Nedovic
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:2726-2735
A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::098ca088182b08fc4220bc5fc60055e8
https://doi.org/10.1109/jssc.2007.908714
https://doi.org/10.1109/jssc.2007.908714
Publikováno v:
ISSCC
We present a leakage current replica (LCR) keeper for dynamic domino gates that uses an analog current mirror to replicate the leakage current of a dynamic gate pull-down stack and thus tracks process, voltage, and temperature. The proposed keeper ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::862112f367f3a3c6bc8c96b3dc54a162
https://doi.org/10.1109/jssc.2006.885051
https://doi.org/10.1109/jssc.2006.885051
Autor:
Nestor Tzartzanis, William W. Walker
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:2141-2147
We present a new on-chip signaling method that relies on differential current-mode sensing to improve both delay and energy dissipation compared to conventional inverter repeaters. The proposed method can be used for point-to-point as well as N-to-1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51fa5e2511a85d4e4d4b07b345cfb8fd
https://doi.org/10.1109/jssc.2005.857351
https://doi.org/10.1109/jssc.2005.857351
Autor:
H. Tamura, Satoshi Ide, Yukito Tsunoda, Yasumoto Tomita, Tadashi Ikeuchi, Scott McLeod, Nestor Tzartzanis, Yoshiyasu Doi, Satoshi Matsubara, Nikola Nedovic, Takayuki Shibasaki, Naoki Kuwata, Kouichi Kanda, Takayuki Hamada, T. Yamamoto, Mariko Sugawara, Tetsuji Yamabana, Junji Ogawa, Samir Parikh, William F. Walker, Anders Kristensson, Masaya Kibune, Subodh M. Reddy
Publikováno v:
2009 Annual IEEE Compound Semiconductor Integrated Circuit Symposium.
A 2 x 21.5-22.3 Gb/s to 4 x 10.7-11.2 Gb/s SFI5.2 compliant two-chip SerDes for a 40 Gb/s optical transponder module has been fabricated in 65 nm 12-metal CMOS. The deserializer receives 2 x 20 Gb/s data from a TIA and outputs SFI 5.2 4 x 10 Gb/s dat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b74d8db72062720fbd7c5768fd3a8431
https://doi.org/10.1109/csics.2009.5315637
https://doi.org/10.1109/csics.2009.5315637
Autor:
Hirotaka Tamura, Nestor Tzartzanis, Y. Okaniwa, M. Wiklund, Y. Mizutani, F.M. Rotella, Tadahiro Kuroda, Junji Ogawa, William F. Walker, Nikola Nedovic
Publikováno v:
ISSCC
A 3times oversampling CDR and 1:16 DEMUX occupies 0.8 times 1.8mm2 in a 90nm CMOS process. The chip operates at 40 to 44Gb/s and dissipates 0.91W. Input data is sampled using a 24-phase distributed VCO and a digital CDR recovers 16 bits and a 2.5GHz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e84939ec731fe30eea18ac1d500c5b34
https://doi.org/10.1109/isscc.2007.373375
https://doi.org/10.1109/isscc.2007.373375
Autor:
William W. Walker, Nestor Tzartzanis
Publikováno v:
ISSCC
A reversible 24-phase closed-loop distributed VCO is implemented in 90nm 10M triple-well 1.2V CMOS using co-planar transmission lines as delay elements. The measured tuning range is 10.4 to 11.4GHz, the phase noise is -96.65dBc/Hz at 1MHz offset, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f62e6462ca7cce1477ac0947290310dc
https://doi.org/10.1109/isscc.2006.1696309
https://doi.org/10.1109/isscc.2006.1696309
Autor:
Nestor Tzartzanis, D. Yamazaki, William W. Walker, Masaya Kibune, H. Tamura, Y. Okaniwa, Tadahiro Kuroda, Tsz-Shing Cheung, Junji Ogawa
Publikováno v:
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2 V supply was designed and fabricated in 0.11 /spl mu/m CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a322cafe273007f2be4d870909e41dcd
https://doi.org/10.1109/vlsic.2004.1346558
https://doi.org/10.1109/vlsic.2004.1346558
Autor:
William W. Walker, Nestor Tzartzanis
Publikováno v:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
A register file read-out method that relies on differential current-mode sensing, while using single-ended bit lines, is presented. This method improves noise immunity, access, and cycle time compared to dynamic approaches. A 34/spl times/64-bit, 10R
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::980afdd5710ec3094e5bc3cc87e6db15
https://doi.org/10.1109/isscc.2004.1332816
https://doi.org/10.1109/isscc.2004.1332816