Zobrazeno 1 - 10
of 157
pro vyhledávání: '"Nemirovsky M"'
Autor:
Немировский, М. В., Nemirovsky, M. V.
The master's dissertation is devoted to the study of municipal practices of network interaction in education organizations in Yekaterinburg and development of technologies for their development. The dissertation considers the conceptual and regulator
Externí odkaz:
http://elar.urfu.ru/handle/10995/93318
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Scopus-Elsevier
Universitat Politècnica de Catalunya (UPC)
Scopus-Elsevier
Estimating available network resources is fundamental when adapting the sending rate both at the application and transport layer. Traditional approaches either rely on active probing techniques or iteratively adapting the average sending rate, as is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::86bb8a4566574d103bba0e836d4fa35b
http://hdl.handle.net/2117/340652
http://hdl.handle.net/2117/340652
Autor:
Nemirovsky, M. V.
Магистерская диссертация посвящена изучению муниципальных практик сетевого взаимодействия в общеобразовательных организациях г. Ека
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od_______917::6a33fc369f8c05dbd72fe6b50354b032
https://hdl.handle.net/10995/93318
https://hdl.handle.net/10995/93318
Autor:
Nemirovsky M., Tullsen D.M.
Publikováno v:
Synthesis Lectures on Computer Architecture
Publikováno v:
Immunology. Mar74, Vol. 26 Issue 3, p477-488. 12p.
Akademický článek
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Autor:
Abadal, S., Cabellos-Aparicio, A., Lázaro, J. A., Nemirovsky, M., Alarcón, E., Josep Solé-Pareta
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Scopus-Elsevier
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
Scopus-Elsevier
Recercat. Dipósit de la Recerca de Catalunya
instname
In the last decade, the field of microprocessor architecture has seen the rise of multicore processors, which consist of the interconnection of a set of independent processing units or cores in the same chip. As the number of cores per multiprocessor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::87d6d37b2c027d28e31eafe7a257db66
http://hdl.handle.net/2117/19576
http://hdl.handle.net/2117/19576
Autor:
Katrinis, K., Syrivelis, D., Pnevmatikatos, D., Zervas, G., Theodoropoulos, D., Koutsopoulos, I., Hasharoni, K., Raho, D., Pinto, C., Espina, F., Lopez-Buedo, S., Chen, Q., Nemirovsky, M., Roca, D., Klos, H., Berends, T.
Publikováno v:
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE); 2016, p690-695, 6p
Publikováno v:
2015 Fourth European Workshop on Software Defined Networks; 2015, p67-72, 6p
Publikováno v:
2014 IEEE 19th International Workshop on Computer Aided Modeling & Design of Communication Links & Networks (CAMAD); 2014, p325-329, 5p