Controllable Molecular Modulation of Conductivity in Silicon-Based Devices

Autor: David A. Corley, Neil Di Spigna, Meng Lu, Tao He, Jianli He, James M. Tour, Paul D. Franzon, David P. Nackashi

Publikováno v: Journal of the American Chemical Society. 131:10023-10030

The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping be

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d02618270e339aa8ffce9f5d620b2c0d
https://doi.org/10.1021/ja9002537

Uniformity analysis of wafer scale sub-25nm wide nanowire array nanoimprint mold fabricated by PEDAL process

Autor: Sachin R. Sonkusale, Neil Di Spigna, Paul D. Franzon

Publikováno v: Microelectronic Engineering. 84:1523-1527

In earlier publications [S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, E. Physica, Low Dimensional Systems and Nanostructures 28 (2005) 107-114; S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9cc3830016f251c32fa28a495e0f5216
https://doi.org/10.1016/j.mee.2007.01.210

Fabrication of wafer scale, aligned sub-25nm nanowire and nanowire templates using planar edge defined alternate layer process

Autor: Sachin R. Sonkusale, David P. Nackashi, Neil Di Spigna, Paul D. Franzon, Mark Johnson, D.W. Barlage, C.J. Amsinck

Publikováno v: Physica E: Low-dimensional Systems and Nanostructures. 28:107-114

We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and h

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1fbe86d672f7257bde147d4fd8873758
https://doi.org/10.1016/j.physe.2005.01.010

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates

Autor: Daniel Schinke, Neil Di Spigna, Veena Misra, Srikant Jayanti, Paul D. Franzon

Publikováno v: IFIP Advances in Information and Communication Technology
20th International Conference on Very Large Scale Integration (VLSI-SoC)
20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.217-233, ⟨10.1007/978-3-642-45073-0_12⟩
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design ISBN: 9783642450723
VLSI-SoC (Selected Papers)

International audience; The operation of a novel unified memory device using two floating-gates is described through experimental characterization of a fabricated proof-of-concept device and confirmed through simulation. The dynamic, nonvolatile, and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::822c10713c4d5ffba46193d86ab741f5
https://hal.inria.fr/hal-01456958/file/978-3-642-45073-0_12_Chapter.pdf

Scaling constraints in nanoelectronic random-access memories

Autor: Neil Di Spigna, C.J. Amsinck, Paul D. Franzon, David P. Nackashi

Publikováno v: Nanotechnology. 16(10)

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1b395ddd8b13f4ddfb7006b01ba980d8
https://pubmed.ncbi.nlm.nih.gov/20818005