Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Natsuki Kushiyama"'
Autor:
R. Clark, C. Tan, G. Coussens, Natsuki Kushiyama, J. Lin, L. Martin, F. Perner, K. Cham, M. Leonard
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:1286-1290
An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-l
Autor:
Mark Horowitz, Satoru Takase, Matthew Murdy Griffin, Victor E. Lee, D. Stark, John B. Dillon, Thomas H. Lee, Shigeo Ohshima, Natsuki Kushiyama, Tohru Furuyama, A. Chan, R.M. Barth, H. Noji, Kiyofumi Sakurai, James A. Gasbarro
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:490-498
A 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate was developed. This high data rate was achieved by designing a DRAM core with a very high internal column bandwidth, and coupling this core with a block-oriented, small-swing, synchronous interfac
Autor:
Y. Takeyama, Yuki Fujimura, Akira Katayama, Osamu Hirabayashi, A. Suzuki, Y. Shizuki, Keiichi Kushida, G. Fukano, Tadahiro Sasaki, T. Nakazato, Atsushi Kawasumi, Tomoaki Yabe, Natsuki Kushiyama
Publikováno v:
ISSCC
A 512Kb dual-power-supply SRAM is fabricated in 40nm CMOS with 0.179µm2 cell, which is 10% smaller than the SRAM scaling trend. The smaller cell size is realized by channel area saving. To improve the cell stability of the small channel area cell, w
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:479-483
A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 mu m twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random acce
Autor:
T. Furuyuma, Victor E. Lee, Kiyofumi Sakurai, Satoru Takase, Natsuki Kushiyama, Mark Horowitz, James A. Gasbarro, Wingyu Leung, D. Stark, Shigeo Ohshima, Matthew Murdy Griffin, Winston South San Francisco Lee, B. Barth, John B. Dillon
Publikováno v:
1992 Symposium on VLSI Circuits Digest of Technical Papers.
A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a
Autor:
M. Ezawa, T. Watanabe, S. Doi, Tohru Furuyama, T. Yoshida, Natsuki Kushiyama, H. Noji, M. Kataoka
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
A simple and practical wafer burn-in (WBI) technology is described. This technology effectively screens reliability failures of random access memories on a wafer, prior to die-sorting. As a result, obtaining "known-good" RAM chips becomes much more r
Autor:
Natsuki Kushiyama, G. Coussens, C. Tan, M. Leonard, J. Lin, K. Cham, K. Chiu, F. Pemer, L. Martin, R. Clark
Publikováno v:
Proceedings ISSCC '95 - International Solid-State Circuits Conference.
This SRAM explores the feasibility of the mid-capacity, wideword, very high-speed embedded memories for the over-200 MHz generation of MPUs. The SRAM is fabricated in a 0.35 /spl mu/m CMOS quadruple-metal process. It has 1 Mb capacity and 256 b of fu
Autor:
Natsuki Kushiyama, Yohji Watanabe, Y. Nagahama, Kazuyoshi Muraoka, Tohru Furuyama, Takashi Ohsawa
Publikováno v:
Digest of Technical Papers., 1990 Symposium on VLSI Circuits.
A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than
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