Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Nathaniel A. Conos"'
Autor:
Youngmin Shin, Hanif Fatemi, Nathaniel A. Conos, Yun Heo, Seung-jae Jung, Kelvin Le, Jong-Pil Lee, Moon-su Kim
Publikováno v:
DATE
As process technologies are scaled down, interconnect delay becomes major component of entire path delay, and vias represent a significant portion of the interconnect delay. In this paper, a novel variation-aware delay computation method for vias is
Publikováno v:
ICASSP
Modern applications, such as video and audio processing, employ many licnear transforms and filters, such as the discrete cosine transform (DCT) and fast Fourier transform (FFT). There is a need to drastically reduce the energy consumption of these a
Publikováno v:
IFIP Advances in Information and Communication Technology ISBN: 9783319237985
VLSI-SoC (Selected Papers)
VLSI-SoC (Selected Papers)
We present a gate sizing approach to efficiently utilize gate switching activity (SA) and gate input vector control leakage (IVC) uncertainty factors in the objective function in order enable more efficient power and speed yield trade-offs. Our algor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::487f4db50b540f34ae30ff20d6c93b87
https://doi.org/10.1007/978-3-319-23799-2_2
https://doi.org/10.1007/978-3-319-23799-2_2
Publikováno v:
ASAP
Customization and adaptation have emerged as the most effective paradigms for energy minimization. We em- ploy these paradigms to address coordinated power gating and dynamic voltage scaling for energy minimization of real-time tasks in both applicat
Publikováno v:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014.
Autor:
Miodrag Potkonjak, Nathaniel A. Conos
Publikováno v:
ICCD
Accurate thermal knowledge is essential for achieving ultra low power in deep sub-micron CMOS technology, as it affects gate speed linearly and leakage exponentially. We propose a temperature-aware synthesis technique that efficiently utilizes input
Publikováno v:
VLSI-SoC
We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we int
Publikováno v:
PATMOS
Near-Threshold Computing (NTC) shows potential to provide significant energy efficiency improvements as it alleviates the impact of leakage in modern deep sub-micron CMOS technology. As the gap between supply and threshold voltage shrink, however, th