Zobrazeno 1 - 10
of 44
pro vyhledávání: '"Nathalie Revil"'
Autor:
G. Bertrand, E. Granger, A. Giry, X. Garros, Emmanuel Vincent, J. Lugo, J. Cluzel, Xavier Federspiel, V. Knopik, A. Divay, Florian Cacho, F. Gaillard, Nathalie Revil
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
A robust and low cost Si RFSOI Power Transistor which can deliver +31dBm output power with 74% of Power Added Efficiency (PAE) and 18dB of Gain has been optimized for 4G & 5G sub-6GHz Power Amplifier (PA). By means of innovative characterizations com
Autor:
M. Buczko, A. Juge, Frederic Gianesello, S. Gachon, E. Granger, G. Bertrand, A. Monroy, V. Vialla, L. Rolland, Jeff Nowakowski, Nathalie Revil, M. Coly, Daniel Gloria, J. P. Aubert, E. Canderle
Publikováno v:
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF).
RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, CMOS Silicon-on-insulator (SOI) has emerged over the pas
Autor:
L. Depoyan, Alain Chantre, S. Montusclat, Malick Diop, Pascal Chevalier, M. Buczko, C. Leyris, Sorin P. Voinigescu, K.H.K. Yau, A. Margain, N. Derrier, S. Boret, S.T. Nicolson, Nicolas Loubet, S. Pruvost, G. Avenier, Nathalie Revil, Didier Dutartre, J. Bouvier, Daniel Gloria, G. Troillard
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2312-2321
This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission
Publikováno v:
Microelectronics Reliability. 48:1198-1201
A critical process aspect of the bipolar device is the oxide isolation between the emitter and the extrinsic base. Indeed, it is a well known fact that the emitter–base junction degradation is mainly due to interface states generation underneath ox
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 6:154-162
A new degradation behavior for heterojunction bipolar transistors under reverse base-emitter junction stress is presented and discussed. Hot carrier injection triggered a correlated decrease of both the base and collector-currents in the first stress
Autor:
Emmanuel Vincent, F. Perrier, M. Denais, Nathalie Revil, Chittoor Parthasarathy, Vincent Huard, Alain Bravaix, Didier Goguenheim
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, 2005, 45 (9-11), pp.1370-1375. ⟨10.1016/j.microrel.2005.07.023⟩
Microelectronics Reliability, 2005, 45 (9-11), pp.1370-1375. ⟨10.1016/j.microrel.2005.07.023⟩
International audience; Permanent damage induced by Channel Hot-Carrier (CHC) injections have been distinguished from the charge-discharge of near-interface traps in ultra-thin gate-oxide (1.6nm) MOSFETs. It is shown that usual DC accelerating techni
Autor:
G. Ribes, M. Denais, F. Perrier, Nathalie Revil, Vincent Huard, Alain Bravaix, Chittoor Parthasarathy
Publikováno v:
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability, 2004, IEEE Transactions on Device and Materials Reliability, 4 (4), pp.715-722. ⟨10.1109/TDMR.2004.840856⟩
IEEE Transactions on Device and Materials Reliability, 2004, IEEE Transactions on Device and Materials Reliability, 4 (4), pp.715-722. ⟨10.1109/TDMR.2004.840856⟩
International audience; This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, 2004, Microelectronic Engineering, 72 (1-4), pp.106-111. ⟨10.1016/j.mee.2003.12.025⟩
Microelectronic Engineering, 2004, Microelectronic Engineering, 72 (1-4), pp.106-111. ⟨10.1016/j.mee.2003.12.025⟩
International audience; Hot-carrier (HC) degradation in PMOSFETs with thin (Tox = 2 nm) and thick (6.5 nm) gate-oxides are investigated as they show very different damage mechanisms when electrons or holes are involved. It is shown for the first time
Autor:
Michel Houssa, Chittoor Parthasarathy, JL Autran, Marc Aoulaiche, Nathalie Revil, Emmanuel Vincent
Publikováno v:
Journal of Applied Physics. 95:2786-2791
The decrease of the threshold voltage Vth of hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed that accounts f
Publikováno v:
Journal of Non-Crystalline Solids. 322:100-104
The decrease of the threshold voltage of p-channel metal-oxide-semiconductor field effect transistors with ultrathin (2 nm) oxynitride layers is studied, during negative gate bias stress at high temperature (125 °C). It is shown that the degradation