Zobrazeno 1 - 10
of 39
pro vyhledávání: '"Natarajan, Mahadeva Iyer"'
Publikováno v:
2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
A matching theorem for the transmission-line based (TMLB) pi-type ESD circuit is found. To return the origin, the total degrees rotated by the matching circuit at the matching frequency is equal to pi or several times greater than pi. Based on this t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5605d723ea747549ddb9bdc8259b5abd
https://doi.org/10.1109/ipfa49335.2020.9260589
https://doi.org/10.1109/ipfa49335.2020.9260589
Publikováno v:
IRPS
A rigorous electrothermal model that describes and correlate the behavior of the ESD devices during TLP and HBM stress conditions for various device types is developed, nearly five decades after well-known Wunsch-Bell and Tasca models.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::414daf9ccaef8d776ce2ec4ef9974d8f
https://doi.org/10.1109/irps.2019.8720576
https://doi.org/10.1109/irps.2019.8720576
Publikováno v:
IRPS
Physical understanding of the interaction of junction depth and the location of different Drain-side N-type implants on the holding-voltage of LDNMOS is presented. Using N-type well implants to modulate the junction depth, width and doping concentrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2fae4c378b42d9470f247835e99f1b4
https://doi.org/10.1109/irps.2019.8720522
https://doi.org/10.1109/irps.2019.8720522
Publikováno v:
IEEE Electron Device Letters. 38:1583-1585
For the first time, the influence of fast pulse induced skin effect on the current distribution inside the grounded-gate NMOS (GGNMOS) is reported. The skin effect results in the current crowding at the finger edges of the GGNMOS, leading to the high
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f5f16e71ce3fa67e4769124a70d8b6c
https://doi.org/10.1109/led.2017.2751418
https://doi.org/10.1109/led.2017.2751418
Publikováno v:
IEEE Electron Device Letters. 38:952-954
Physics of correlation between standard ESD testing and transmission line pulse test results on semiconductor devices using a simple resistor (R) inductor (L) capacitor (C) circuit model approach is presented. The correlation is not a constant factor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da099b752679c17cb6caa80a5c335a30
https://doi.org/10.1109/led.2017.2708420
https://doi.org/10.1109/led.2017.2708420
Publikováno v:
IEEE Electron Device Letters. 38:623-625
A novel high electrostatic discharge (ESD), robust fully salicided 5-V integrated CMOS power MOSFET design is developed and demonstrated without the use of conventional salicide blocking ballast resistor. This scheme builds the ballast resistors on t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::caa9ef7fff597a66b72caf9f474f463c
https://doi.org/10.1109/led.2017.2686638
https://doi.org/10.1109/led.2017.2686638
Publikováno v:
2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
A simple and useful scheme to improve the ESD performance of HV LDNMOS is reported. Removing the N+ implant from the drain, the silicide to NDDD junction of HV LDNMOS becomes a Schottky barrier. This modification can incorporate a Schottky pnp bipola
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca39e30f4a5c39ecf83c672c085c699e
https://doi.org/10.23919/eosesd.2017.8073447
https://doi.org/10.23919/eosesd.2017.8073447
Autor:
Edmund Banghart, Shesh Mani Pandey, Jian-Hsing Lee, Richard A. Poro, Nicholas Hogle, Natarajan Mahadeva Iyer, Manjunatha Prabhu, Ronghua Yu, Ephrem Gebreselaie, You Li, Robert Gauthier
Publikováno v:
2017 39th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).
A very simple and useful scheme to enhance the ESD performance of the nFinFET is proposed. By incorporating the N-Well (NW) with the nFinFET, it becomes a low holding-voltage SCR if the NW contact is ohmic and becomes a high holding-voltage SCR if th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b7c346eb5f8c3019aa00b6ff8cb5a0a
https://doi.org/10.23919/eosesd.2017.8073416
https://doi.org/10.23919/eosesd.2017.8073416
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
An abnormal I/O failure caused by the board-capacitor (BC) of the HBM tester is reported. Without any discharge component, the BC was charged up to the high voltage during the HBM test of the No-Connect pin. As the relay switches to the next pin to d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d8b3aca3947277ab0639e33fa0c271f
https://doi.org/10.1109/irps.2017.7936369
https://doi.org/10.1109/irps.2017.7936369
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
A novel diode structure is successfully designed for the first time to protect the power line against the ESD stress condition in the high voltage (HV) CMOS technology nodes. Controlled by the voltage difference between V DD and signal, the depletion
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b189fb99557d7f7343d0943dd7651d5
https://doi.org/10.1109/irps.2017.7936299
https://doi.org/10.1109/irps.2017.7936299