Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Nastaran Nemati"'
Publikováno v:
MWSCAS
This work proposes automatic test pattern generation (ATPG) for Null Convention Logic (NCL). NCL is a robust asynchronous paradigm that introduces new challenges to test and testability algorithms due to the lack of a clock signal and the presence of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::039e4b3bb5c1568c12a861c199d0584e
https://doi.org/10.1109/mwscas.2016.7870032
https://doi.org/10.1109/mwscas.2016.7870032
Publikováno v:
ISCAS
This work proposes asynchronous interleaved scan architecture (AISA) intended for the internal structure of online Built-in Self-test for Null Convention Logic (NCL) circuits. NCL is a robust asynchronous paradigm which can target devices for long-li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8686de93dc2a130a7f9c87a58d3b9c8f
https://doi.org/10.1109/iscas.2016.7527348
https://doi.org/10.1109/iscas.2016.7527348
Publikováno v:
ISCAS
Asynchronous design is predicted to have a significant place in the future due to benefits of speed, power consumption, and design. Null Convention Logic (NCL) is a subcategory of asynchronous design that results in the most reliable and low-power as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52b944a0b33c050d3a301e4d792abd50
https://doi.org/10.1109/iscas.2014.6865492
https://doi.org/10.1109/iscas.2014.6865492
Autor:
Nastaran Nemati, Zainalabedin Navabi
Publikováno v:
Asian Test Symposium
Test and testability are essential concerns for design in any abstraction level, and are even more challenging for high level designs. Because of complexity of today's designs, design at ESL (electronic system level) using transaction level modeling
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2f5122c2fbefbdce3793e6db1ed63d4
https://doi.org/10.1109/ats.2011.103
https://doi.org/10.1109/ats.2011.103
Publikováno v:
EWDTS
As digital systems become more complex, testing these complicated systems faces more challenges. One extreme is to use an ATE that tests our chip under control of a complex high level test program. Unfortunately the ATE is incapable of performing at-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a30882da21fe6d84e7ae759ed263d0e
https://doi.org/10.1109/ewdts.2010.5742156
https://doi.org/10.1109/ewdts.2010.5742156
Publikováno v:
EWDTS
This paper discusses a set of functions which are added to Verilog through its PLI interface that facilitates test and application of test programs to designs at the RT level. Using this package, not only enables a designer to apply test programs to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f62c00ebbaf35a2d0ef3076ac29bbdf
https://doi.org/10.1109/ewdts.2010.5742076
https://doi.org/10.1109/ewdts.2010.5742076
Publikováno v:
EWDTS
Optimized test generation techniques are required to overcome the ever increasing test cost of digital systems. In this work a near optimal machine learning based approach is proposed to improve the random test generation techniques. The improvements
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b1954d0423750f65adcfccc8750a825
https://doi.org/10.1109/ewdts.2010.5742082
https://doi.org/10.1109/ewdts.2010.5742082
Publikováno v:
DFT
Optimizing the BIST configuration based on the characteristics of the design under test is a complicated and challenging work for test engineers. Since this problem has multiple optimization factors, trapping in local optimums is very plausible. Ther
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e08912d9a902987f68c6e05388f01a2b
https://doi.org/10.1109/dft.2009.55
https://doi.org/10.1109/dft.2009.55
Publikováno v:
2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era.
The complexities of designs are increasing progressively and the computational parts have become larger, so communications between various design modules have come to be more complicated and critical. This complexity makes the designs difficult to te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc304e121fb75065dff68841ac1f11d5
https://doi.org/10.1109/dtis.2009.4938015
https://doi.org/10.1109/dtis.2009.4938015