Výsledky vyhledávání - "Nasser Erfani Majd"

Akademický článek

Low-clock-speed time-interleaved architecture for a polar delta–sigma modulator transmitter

Publikováno v: ETRI Journal, Vol 45, Iss 1, Pp 150-162 (2023)

The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software-defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitt

Externí odkaz: https://doaj.org/article/a239407fced548fca4b96582cc2e3359

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Interleaved converter with ultra-high voltage gain for DC microgrid application

Autor: Rezvan Fani, Nasser Erfani Majd

Publikováno v: International Journal of Electronics. :1-20

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::13b719ae087e2e16c40152ec705467c2
https://doi.org/10.1080/00207217.2022.2164077

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Low‐clock‐speed time‐interleaved architecture for a polar delta–sigma modulator transmitter

Autor: Nasser Erfani Majd, Rezvan Fani

Publikováno v: ETRI Journal. 45:150-162

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7ba34b247ee792f1eb9484ed7f4a6bef
https://doi.org/10.4218/etrij.2021-0443

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An interleaved ultra-high step up DC–DC converter with low voltage stress

Autor: Rezvan Fani, Nasser Erfani Majd

Publikováno v: Electrical Engineering. 104:3649-3657

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2faaf3053def01cc67e956f81e242ba9
https://doi.org/10.1007/s00202-022-01563-y

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Complexity-Reduced Parallel Time-Interleaved Delta–Sigma Modulator for Transmitter Applications

Autor: Nasser Erfani Majd, Rezvan Fani

Publikováno v: Journal of Circuits, Systems and Computers. 31

High sampling frequency requirement in delta–sigma modulator (DSM) is one of the limiting factors toward its employment in high-frequency application, such as software-defined radio (SDR) transmitters. In this paper, a complexity-reduced parallel t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::71aac129b2c0a8035b71b182ed044f05
https://doi.org/10.1142/s0218126622502413

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Efficiency Improvement of Delta Sigma Modulator-Based Transmitter Using Complex Delta Sigma Modulator and Noise Reduction Loop

Autor: Amin Aeenmehr, Nasser Erfani Majd

Publikováno v: Journal of Circuits, Systems and Computers. 29:2050267

This paper proposes an architecture to enhance coding efficiency (CE) of the Delta Sigma Modulator (DSM) transmitters. In this architecture, a complex–low pass delta sigma modulator (LPDSM) is used instead of existing Cartesian–LPDSM and polar–

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f1d8c7ae2ab7c65e89fe16789b6c98e0
https://doi.org/10.1142/s0218126620502679

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Bandwidth enhancement in delta sigma modulator transmitter using low complexity time-interleaved parallel delta sigma modulator

Autor: Abbas Mohammadi, Nasser Erfani Majd, Hassan Ghafoorifard

Publikováno v: AEU - International Journal of Electronics and Communications. 69:1032-1038

In this paper, the bandwidth of the delta sigma modulator (DSM)-transmitter is improved using low complexity time-interleaved DSM. The high clock speed requirement of DSM is the main limitation to increase the signal bandwidth in DSM-transmitter. In

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::734ac74c3f380cea0aba7042fdf0685c
https://doi.org/10.1016/j.aeue.2015.04.001

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An ultra low power and low complexity all digital PLL with a high resolution digitally controlled oscillator

Autor: Mohammad Bagher Ghaznavi-Ghoushchi, Mojtaba Lotfizad, Arash Abadian, Nasser Erfani Majd

Publikováno v: IEICE Electronics Express. 8:1801-1807

In this letter, a new all digital phase locked loop (ADPLL) is proposed. The proposed ADPLL is introduced a new locking procedure with low complexity which results in an ultra low power design. The design uses only two up-down counters for finding th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b41aa6347f733417ab5f01544d2c7731
https://doi.org/10.1587/elex.8.1801

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An ultra low-power digitally controlled oscillator using novel Schmitt-trigger based hysteresis delay cells

Autor: Arash Abadian, Mojtaba Lotfizad, Nasser Erfani Majd, Mohammad Bagher Ghaznavi-Ghoushchi

Publikováno v: IEICE Electronics Express. 8:589-595

In this paper, an ultra low power 15-bit digitally controlled oscillator (DCO) is proposed. The proposed DCO is designed based on a segmental coarse-tuning stage which employs novel Schmitt-trigger based hysteresis delay cells (HDC) as well as digita

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6dcf1509ef081ea270ec144f5b1d7524
https://doi.org/10.1587/elex.8.589

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Coding Efficiency and Bandwidth Enhancement in Polar Delta-Sigma Modulator Transmitter Using Quantization Noise Reduction and Parallel Processing Techniques

Autor: Hassan Ghafoori Fard, Nasser Erfani Majd, Abbas Mohammadi

Publikováno v: Journal of Circuits, Systems and Computers. 26:1750085

This paper introduces an architecture to enhance coding efficiency (CE) and bandwidth of the delta-sigma modulator (DSM) transmitters. In this architecture a low-pass envelope DSM (LPEDSM) is used instead of the traditional Cartesian low-pass DSM (LP

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9b63f4cd466ef392ebd7098ab5565918
https://doi.org/10.1142/s0218126617500852

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