Zobrazeno 1 - 10
of 42
pro vyhledávání: '"Narendra Shenoy"'
Autor:
Tukaram U. Shinde, Vishwanath H. Dalvi, Channamallikarjun S. Mathpati, Narendra Shenoy, Sudhir V. Panse, Jyeshtharaj B. Joshi
Publikováno v:
Chemical Engineering and Processing - Process Intensification. 180:108791
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f73de326b06c76420bd12197609df58c
https://doi.org/10.1016/j.cep.2022.108791
https://doi.org/10.1016/j.cep.2022.108791
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1522-1533
This paper quantifies the approximation error when results obtained by Clark (1961) are employed to compute the maximum (max) of Gaussian random variables, which is a fundamental operation in statistical timing. We show that a finite lookup table can
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3cf568a747a78e054b222e6e089364f
https://doi.org/10.1109/tcad.2007.893544
https://doi.org/10.1109/tcad.2007.893544
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14:1140-1146
In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experime
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::505efcbc378408c5c11090ce67ea3474
https://doi.org/10.1109/tvlsi.2006.884166
https://doi.org/10.1109/tvlsi.2006.884166
Publikováno v:
ASP-DAC
Minimum spanning tree problem is a very important problem in VLSI CAD. Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7745dd50d5ddef73746fe72158c6bbbd
https://doi.org/10.1016/s0020-0190(01)00232-0
https://doi.org/10.1016/s0020-0190(01)00232-0
Autor:
Narendra Shenoy
Publikováno v:
Integration. 22:1-21
Retiming is a technique for optimizing sequential circuits. It repositions the registers in a circuit leaving the combinational portion of circuitry untouched. The central objective of retiming is to find a circuit with the minimum number of register
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d058d7f5577ce8d1678b62f49d3b9075
https://doi.org/10.1016/s0167-9260(97)00002-3
https://doi.org/10.1016/s0167-9260(97)00002-3
Autor:
Narendra Shenoy, Paul Lo
Publikováno v:
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.
Analog and mixed signal (AMS) circuits play an ever increasing role in semiconductors. In this paper, we provide a brief introduction to the trends in the industry. We use these trends to describe key needs of AMS design. We highlight some of the cha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::36fc8ccad8d583f5a6a156eaa900d55c
https://doi.org/10.1109/icsict.2012.6467827
https://doi.org/10.1109/icsict.2012.6467827
Autor:
Subramanian Rajagopalan, Narendra Shenoy, Shabbir H. Batterywala, Sambuddha Bhattacharya, H.-K.T. Ma
Publikováno v:
ISQED
Sub-wavelength lithography in modern fabrication processes has resulted in a tremendous increase in the number of design rules. Of these, the context dependent design rules are especially hard to adhere to during manual layout creation. Layout legali
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::940cbd34cce0491b4d3818df84044e28
https://doi.org/10.1109/isqed.2008.4479761
https://doi.org/10.1109/isqed.2008.4479761
Autor:
Subramanian Rajagopalan, Narendra Shenoy, H.-K.T. Ma, Sambuddha Bhattacharya, Shabbir H. Batterywala
Publikováno v:
ISQED
Layout migration is an important step in design reuse. This paper presents a cell swapping based methodology to migrate hierarchical layouts from one technology to another. The migrated layouts retain both layout hierarchy and swapped cell sanctity.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35674e353fce7e4881b53835f1abb1ca
https://doi.org/10.1109/isqed.2008.4479775
https://doi.org/10.1109/isqed.2008.4479775
Autor:
Jianfeng Luo, Narendra Shenoy, Shabbir H. Batterywala, Debjit Sinha, Hai Zhou, Subramanian Rajagopalan
Publikováno v:
VLSI Design
This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b133dd0cc98f2af9025a0398471cad7f
https://doi.org/10.1109/vlsid.2007.90
https://doi.org/10.1109/vlsid.2007.90