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Akademický článek

Practical modeling of fluid in ABWR suppression pool for seismic analysis using 3D FEM model

Autor: Shohei ONITSUKA, Yoshihiro GOTO, Tadashi IIJIMA, Naoki OJIMA

Publikováno v: Mechanical Engineering Journal, Vol 4, Iss 3, Pp 17-00152-17-00152 (2017)

This paper presents a practical modeling of the fluid in a suppression pool (SP) for seismic analysis by using three-dimensional finite element method (3D FEM) models of the reactor building of an advanced boiling water reactor (ABWR). We performed a

Externí odkaz: https://doaj.org/article/743eda7865c640f3bd0c805755af2c88

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An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Autor: Shuowei Li, Zule Xu, Tetsuya Iizuka, Naoki Ojima

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:2153-2162

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::72e8f021df69b34d46faa8f4836c5c7b
https://doi.org/10.1109/tvlsi.2021.3122027

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Analysis and simulation of MOSFET-based gate-voltage-independent capacitor

Autor: Shuowei Li, Naoki Ojima, Zule Xu, Tetsuya Iizuka

Publikováno v: Japanese Journal of Applied Physics. 61:064501

In this paper, we analyze the gate capacitance of a MOSFET (Metal–Oxide–Semiconductor Field-Effect Transistor) and propose a method of realizing the capacitance less dependent on the gate voltage. We analyze the mechanism of capacitance formation

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ed33ac369ad9e2ca590d8b4fd39a6fb5
https://doi.org/10.35848/1347-4065/ac6406

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Practical modeling of fluid in ABWR spent fuel pool for seismic analysis using 3D FEM model

Autor: Tadashi Iijima, Shohei Onitsuka, Yoshihiro Goto, Naoki Ojima

Publikováno v: Nuclear Engineering and Design. 331:238-247

Seismic analysis is important for ensuring the integrity of structures in nuclear power plants. This study investigates the practical modeling method of the fluid in a spent fuel pool (SFP) of an advanced boiling water reactor (ABWR) nuclear power pl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1800f3befa6b183f2a84a9ea6edb905e
https://doi.org/10.1016/j.nucengdes.2018.03.002

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Modeling method of element Rayleigh damping for the seismic analysis of a 3D FEM model with multiple damping properties

Autor: Shohei Onitsuka, Naoki Ojima, Yuichi Ushio, Tadashi Iijima

Publikováno v: Journal of Vibration and Control. 24:4065-4077

Damping modeling is important for the accurate evaluation of the seismic response of structures. Our group previously reported a damping modeling method using element Rayleigh damping and evaluated the effectiveness using a simple lumped-mass model w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::416740f4579a12a1223ce81cc2df2f72
https://doi.org/10.1177/1077546317718969

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A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Autor: Zule Xu, Naoki Ojima, Tetsuya Iizuka

Publikováno v: NEWCAS

This paper proposes a synthesizable successive approximation register analog to digital converter (SAR ADC) that consists of only standard cells. In this SAR ADC, analog components such as resistive digital to analog converters (RDAC), a four-input c

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f91aa02a94df112ac2e37d72f5513bd2
https://doi.org/10.1109/newcas44328.2019.8961218

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A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Autor: Tetsuya Iizuka, Kunihiro Asada, Toru Nakura, Naoki Ojima

Publikováno v: IFIP Advances in Information and Communication Technology
26th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC)
26th IFIP/IEEE International Conference on Very Large Scale Integration-System on a Chip (VLSI-SoC), Oct 2018, Verona, Italy. pp.1-13, ⟨10.1007/978-3-030-23425-6_1⟩
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms ISBN: 9783030234249
VLSI-SoC (Selected Papers)

A synthesizable digital LDO implemented with standard-cell-based digital design flow is proposed. The difference between output and reference voltages is converted into delay difference using inverter chains as voltage-controlled delay lines, then co

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ccf6a95e1ff3349129fc1739f69fbcd
https://hal.inria.fr/hal-02321770

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A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

Autor: Tetsuya Iizuka, Toru Nakura, Kunihiro Asada, Naoki Ojima

Publikováno v: VLSI-SoC

This paper proposes a synthesizable digital LDO that is implemented with standard-cell-based digital design flow. With inverter chains as voltage-controlled delay lines, the difference between output and reference voltages is converted into delay dif

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d2de6c03795c7f01c93e11707490cbf6
https://doi.org/10.1109/vlsi-soc.2018.8644879

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