Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Naoki Idani"'
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2373-2382
SUMMARY As VLSI process node continue to shrink, chemical mechanical planarization (CMP) process for copper interconnect has become an essential technique for enabling many-layer interconnection. Recently, Edge-over-Erosion error (EoE-error), which o
Publikováno v:
Physical Review B. 49:22-27
Natural polycrystalline graphite was compressed using a 6-8-type multianvil and a Drickamer cell, and the recovered samples were examined by x-ray diffraction and transmission-electron microscopy. Diamond was formed in the samples from 14\ensuremath{
Autor:
Norihiro Harada, Osamu Yamasaki, Naoki Idani, Toshiyuki Shibuya, Takanori Hiramoto, Daisuke Fukuda, Izumi Nitta, Yuji Kanazawa, Masaru Ito
Publikováno v:
ISQED
Chemical Mechanical Polishing (CMP)-aware design has become important for reliability and yield. Recent work on predictive models for wafer surface planarity of Cu CMP has proven that the variation of wafer surface planarity is impacted by the metal
Autor:
Y. Momiyama, Kazuo Kawamura, Naoki Idani, S. Satoh, H. Fukutome, S. Akiyama, Hiroyuki Ohta, Kazuya Okubo
Publikováno v:
Extended Abstracts of the 2009 International Conference on Solid State Devices and Materials.
Publikováno v:
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials.
Autor:
Motoshu Miyajima, Tetsuya Shirasu, Takahiro Kimura, Akbar Ade Asneil, Tomoji Nakamura, Naoki Idani, Tsuyoshi Kanki, Sakamoto Manabu, Satoshi Takesako
Publikováno v:
2008 International Interconnect Technology Conference.
In order to achieve high throughput Cu-CMP compatible with low step heights in 32nm Node copper interconnect technologies and beyond, we believe it is crucial a passivation layer on the Cu surface in the slurry during the CMP process. We show that th
Autor:
Yoichi Momiyama, Hidenobu Fukutome, Shigeo Satoh, Shinichi Akiyama, Kazuo Kawamura, Naoki Idani, Hiroyuki Ohta, Kazuya Okubo
Publikováno v:
Japanese Journal of Applied Physics. 49:04DC16
We demonstrated an ideal scaling of inversion gate dielectric thickness (T inv) without the decrease in the channel strain of a short-channel planar transistor using a Pt-incorporated fully Ni-silicide (Ni-FUSI)/SiON gate stack. We have achieved driv