Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Naohiko Irie"'
Autor:
Hiroki Ishikuro, Yasufumi Sugimori, Yoshinori Kohama, Kiichi Niitsu, Tadahiro Kuroda, Naohiko Irie, Kenichi Osada
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:1902-1907
This paper discusses analysis and techniques for mitigating interference of an inductive-coupling inter-chip link. Electromagnetic interference from power/signal lines and to SRAM circuits was simulated and measured. In order to verify the interferen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fd9eb4d29863485b22d2cc493c16cc83
https://doi.org/10.1109/tvlsi.2010.2056711
https://doi.org/10.1109/tvlsi.2010.2056711
Autor:
Kiichi Niitsu, Yasufumi Sugimori, Tadahiro Kuroda, Hiroki Ishikuro, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Kazutaka Kasuga
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1238-1243
Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip links for 3-D system integration is introduced for the first time. Misalignment between stacked chips reduces coupling coefficiency of on-chip inductors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7515c06c2a91a8d1b4da7a788025f07b
https://doi.org/10.1109/tvlsi.2009.2020724
https://doi.org/10.1109/tvlsi.2009.2020724
Autor:
Yoshinori Kohama, Makoto Saen, Kenichi Osada, Toshihiro Hattori, Kazutaka Kasuga, Yasufumi Sugimori, Kiichi Niitsu, Naohiko Irie, Atsushi Hasegawa, Tadahiro Kuroda, Itaru Nonomura, Yasuyuki Okuma, Yasuhisa Shimazaki
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:856-862
This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9e3291f63c528be58569a66a482c420
https://doi.org/10.1109/jssc.2010.2040310
https://doi.org/10.1109/jssc.2010.2040310
Autor:
Toshihiro Hattori, Naohiko Irie
Publikováno v:
IEICE Transactions on Electronics. :1232-1239
SoC has driven the evolution of embedded systems or consumer electronics. Multi-core/multi-IP is the key technology to integrate many functions on a SoC for future embedded applications. In this paper, the transition of SoC and its required functions
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::804135a903d51efc7ea225d0e38b95dc
https://doi.org/10.1587/transele.e92.c.1232
https://doi.org/10.1587/transele.e92.c.1232
Autor:
Kenji Kitagawa, Ryohei Yoshida, Naohiko Irie, Keisuke Toyama, Takahiro Irita, Takanobu Tsunoda, Tetsuya Yamada, Motoaki Satoyama
Publikováno v:
IEICE Transactions on Electronics. :523-530
We have developed a hardware accelerator for Java platforms, integrated on a SuperH microprocessor core, using a 130-nm CMOS process. The Java accelerator, a bytecode translation unit (BTU), is tightly coupled with the CPU to share resources. The BTU
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::243a094fa8729beaafaf8d53af4680bd
https://doi.org/10.1093/ietele/e90-c.2.523
https://doi.org/10.1093/ietele/e90-c.2.523
Autor:
K. Hirose, Y. Yasu, Tadashi Hoshi, Naohiko Irie, Toshihiro Hattori, Hiroyuki Mizuno, Tetsuya Yamada, Takahiro Irita, Yasuhisa Shimazaki, Yusuke Kanno, Kazumasa Yanagisawa, Y. Miyairi, Tomoyuki Ishii
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:74-83
Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution support
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c90dfe6de3f4b56a86df7efa1f0ac4b
https://doi.org/10.1109/jssc.2006.885057
https://doi.org/10.1109/jssc.2006.885057
Autor:
Shigenobu Komatsu, Atsushi Hasegawa, Itaru Nonomura, Makoto Saen, Yoshinori Kohama, Toshihiro Hattori, Kenichi Osada, Tadahiro Kuroda, Kiichi Niitsu, Yasufumi Sugimori, Kazutaka Kasuga, Naohiko Irie, Yasuhisa Shimazaki
Publikováno v:
ISSCC
This paper presents a three-dimensional (3D) system integration of a commercial processor and a memory by using inductive coupling. A 90nm CMOS 8-core processor, back-grinded to a thickness of 50µm, is mounted face down on a package by C4 bump. A 65
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5842634bed81d127b291e101454bec8
https://doi.org/10.1109/isscc.2009.4977517
https://doi.org/10.1109/isscc.2009.4977517
Autor:
Hiroki Ishikuro, Kiichi Niitsu, Kenichi Osada, Naohiko Irie, Yoshinori Kohama, Yasufumi Sugimori, Tadahiro Kuroda
Publikováno v:
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94e2333787b709bc912c3f4ebf01b3ae
https://doi.org/10.7567/ssdm.2008.d-2-4
https://doi.org/10.7567/ssdm.2008.d-2-4
Autor:
Tatsuya Kamei, M. Takada, Toshihiro Hattori, K. Hayase, Yuta Yoshida, Shinichi Shibahara, Osamu Nishii, K. Takada, Naohiko Irie
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
We have developed an embedded processor that supports asymmetric multiple processor (AQMP), symmetric multiple processor (SMP), and an AMP/SMP hybrid system. It contains four SH-X3 cores used to support cache coherency from that obtained using an SH-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50b0c9fe523cba5957701d15cb87eb4e
https://doi.org/10.1109/asscc.2007.4425678
https://doi.org/10.1109/asscc.2007.4425678
Autor:
Naohiko Irie, Hiroki Ishikuro, Yoshinori Kohama, Kenichi Osada, Tadahiro Kuroda, Kiichi Niitsu, Yasufumi Sugimori
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
This paper discusses interference of an inductive-coupling link in 65nm CMOS. Electromagnetic interference from power/signal lines and to SRAM was simulated and measured. Interference from power lines for mobile applications (line and space) is small
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a55594fbde0b82ac92ff7878b7aa4197
https://doi.org/10.1109/asscc.2007.4425749
https://doi.org/10.1109/asscc.2007.4425749