Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Naoaki Naka"'
Autor:
Tomoyuki Arai, Takayuki Shibasaki, Yasufumi Sakai, Masahiro Kudo, Naoaki Naka, Atsushi Matsuda, Hirotaka Tamura, Toshihiko Mori, Shigeaki Kawai, Yoichi Koyanagi, Futoshi Terasawa, Hirohito Higashi, Hiroki Miyaoka, Hideki Kano, Yuuki Ogata, Takumi Danjo, Hisakatsu Yamaguchi
Publikováno v:
ISSCC
With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1–3]. To achieve better power efficiency than that o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23280a97d46e34de82127fec64884712
https://doi.org/10.1109/isscc.2016.7417908
https://doi.org/10.1109/isscc.2016.7417908
Autor:
Hirohito Higashi, Atsushi Matsuda, Masahiro Kudo, Kazuhiro Terashima, Shigeaki Kawai, Tomokazu Higuchi, Yutaka Ide, Futoshi Terasawa, Naoaki Naka, Hideki Kano, Noriaki Shirai, Tomoyuki Arai, Hiroki Miyaoka
Publikováno v:
A-SSCC
A low-power and area optimized 28-nm CMOS 28-Gb/s transceiver is presented. The transceiver comprised with one PLL shared with 4 transceiver lanes. To meet the CEI-28G-VSR and CAUI4 (chip-to-module) standards, a 1-tap DFE is employed for the receiver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f249c2d113952965383942ce3a2932d6
https://doi.org/10.1109/asscc.2015.7387468
https://doi.org/10.1109/asscc.2015.7387468